Course11710611453 lectures
Digital Circuits and Systems
Prof. Shankar Balachandran · IIT Madras
Lectures
Week 1
- Introduction
- Basic Boolean Logic
- Boolean Theorems
- Definitions, SoP and Pos
- Algebraic Minimization Examples
- Introduction to Verilog
Week 2
- Universality, Rearranging Truth Tables
- Karnaugh Maps
- K-Map Minimization
- K-Map with Don't cares
- Multiple Output Functions
- Number Systems
Week 3
- Encoders and Decoders
- Multiplexers
- Multiplexer based Circuit Design
- Verilog
- Compiling and Running Verilog - A Demonstration
Week 4
- Sequential Elements
- Gated Latches
- Flipflops
- Verilog - Assign Statement and Instantiation
- Sequential Circuits
Week 5
- CMOS+Electrical Properties
- Delays
- Sequential Element Delays
- More Sequential Circuits
- Introduction to State Machines
- Always Statement in Verilog
Week 6
- Sequential Logic Synthesis
- FSM Design Problems
- State Minimization
- State Assignment
- Timing Sequential Circuits
- Verilog Styles + Sequential Elements
Week 7
- GCD Algorithm
- GCD Machines Datapath
- GCD State Machine
- GCD Top Level Module
- Datapath in Verilog
- Datapath Elements in Verilog
- FSM in Verilog
- Putting it all together
Week 8
- Pipelining
- K-stage Pipeline
- Interleaving and Parallelism
- Blocking and Non-blocking Statements
- Modeling Circuits with Pipelining
Week 9
Syllabus and materials
At NPTEL, as the course publishes them.
Credits and licence
- Institution
- IIT Madras
- Department
- Electronics & Communication Engineering
- Teacher
- Prof. Shankar Balachandran
- Level
- Undergraduate
- Language
- English
- Subjects
- Engineering, Society and politics
- Source
- NPTEL
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- NPTEL gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed
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