Learn · Digital Circuits and Systems
Lecture 10 of 53Week 2
K-Map with Don't cares
Prof. Shankar Balachandran · IIT Madras
Credits and licence
- From
- Digital Circuits and Systems, IIT Madras (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- Teens profiles and older. How courses are placed
All the lectures
- Introduction
- Basic Boolean Logic
- Boolean Theorems
- Definitions, SoP and Pos
- Algebraic Minimization Examples
- Introduction to Verilog
- Universality, Rearranging Truth Tables
- Karnaugh Maps
- K-Map Minimization
- K-Map with Don't cares
- Multiple Output Functions
- Number Systems
- Encoders and Decoders
- Multiplexers
- Multiplexer based Circuit Design
- Verilog
- Compiling and Running Verilog - A Demonstration
- Sequential Elements
- Gated Latches
- Flipflops
- Verilog - Assign Statement and Instantiation
- Sequential Circuits
- CMOS+Electrical Properties
- Delays
- Sequential Element Delays
- More Sequential Circuits
- Introduction to State Machines
- Always Statement in Verilog
- Sequential Logic Synthesis
- FSM Design Problems
- State Minimization
- State Assignment
- Timing Sequential Circuits
- Verilog Styles + Sequential Elements
- GCD Algorithm
- GCD Machines Datapath
- GCD State Machine
- GCD Top Level Module
- Datapath in Verilog
- Datapath Elements in Verilog
- FSM in Verilog
- Putting it all together
- Pipelining
- K-stage Pipeline
- Interleaving and Parallelism
- Blocking and Non-blocking Statements
- Modeling Circuits with Pipelining
- Signed Number Representation
- Signed Number Addition
- Adder/Subtracter
- Fast Adders
- Multiplication
- Closing Remarks