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Course11710610934 lectures

Advanced Logic Synthesis

Dhiraj Taneja · IIT Madras

Start with lecture 1 At NPTEL

Lectures

MOS Transistor

  1. MOS Transistor Video
  2. MOS Transistor - Detailed Study Video

Digital timing in CMOS

  1. Combinational Circuits & layout Video
  2. Delay Video
  3. Sequential Circuits Video
  4. Logical Effort Video
  5. Circuit Families Video

Process Of Synthesis, Libraries And Technology Mapping

  1. Lab-01 Video
  2. Lab-02 Video
  3. Lab-03 Video
  4. Lab-04 Video
  5. Introduction to Synthesis Video
  6. Libraries Video
  7. RTL Coding for Synthesis Video
  8. Reading Design in DC Video
  9. Design Environment Video
  10. Design Constraints Video
  11. Compile Flow and stratergies Video
  12. Analysis and Reporting Video

Advanced Synthesis flow

  1. Lab-05 Video
  2. Advanced Synthesis Techniques Video
  3. Datapath Extraction Guidelines Video
  4. Power - Methodology and Analysis Video

Timing Analysis

  1. Lab-06 Video
  2. Lab-07 Video
  3. Lab-08 Video
  4. Lab-09 Video
  5. Static Timing Analysis - Concepts and Flow Video
  6. Interconnects and Delay calculation Video
  7. Clock and Exceptions Video
  8. On Chip Variation Video
  9. Introduction to Crosstalk Video
  10. Gaussian / Normal Distribution Video
  11. Equivalence Checking / Formal Verification Video

Syllabus and materials

At NPTEL, as the course publishes them.

Credits and licence

Institution
IIT Madras
Department
Electronics & Communication Engineering
Teacher
Dhiraj Taneja
Level
Undergraduate
Language
English
Subjects
Engineering, Society and politics
Source
NPTEL
Licence
CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
Attribution
NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
Who can watch
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