Learn · Advanced Logic Synthesis
Lecture 5 of 34Digital timing in CMOS
Sequential Circuits
Dhiraj Taneja · IIT Madras
Credits and licence
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- Advanced Logic Synthesis, IIT Madras (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
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- Teens profiles and older. How courses are placed
All the lectures
- MOS Transistor
- MOS Transistor - Detailed Study
- Combinational Circuits & layout
- Delay
- Sequential Circuits
- Logical Effort
- Circuit Families
- Lab-01
- Lab-02
- Lab-03
- Lab-04
- Introduction to Synthesis
- Libraries
- RTL Coding for Synthesis
- Reading Design in DC
- Design Environment
- Design Constraints
- Compile Flow and stratergies
- Analysis and Reporting
- Lab-05
- Advanced Synthesis Techniques
- Datapath Extraction Guidelines
- Power - Methodology and Analysis
- Lab-06
- Lab-07
- Lab-08
- Lab-09
- Static Timing Analysis - Concepts and Flow
- Interconnects and Delay calculation
- Clock and Exceptions
- On Chip Variation
- Introduction to Crosstalk
- Gaussian / Normal Distribution
- Equivalence Checking / Formal Verification