Course10810618465 lectures
Phase-locked loops
Prof. Saurabh Saxena · IIT Madras
About
This course will emphasize on developing intuition behind frequency synthesizer design, learning mathematical basis behind operation, and realizing PLLs at architecture and circuit level. The students will be exposed to state-of-the-art frequency synthesis techniques used in analog/digital integer-N PLLs.
This course will equip students with skills to analyze, debug, and evaluate a PLL design at analytical and transistor levels both. The students will be able to use their knowledge and skills while generating a clock signal in a power-efficient manner for requirements of a synchronous system.
Intended audience: B.Tech (6th semester onwards), M.Tech./M.S./Ph.D. (1st semester onwards)
Prerequisites: EE3002 (http://www.ee.iitm.ac.in/vlsi/courses/ee3002_2017/start)INTENDED AUDIENCE: B.Tech (6th semester onwards), M.Tech./M.S./Ph.D. (1st semester onwards)
Lectures
Week 1
- Course Introduction and Motivation: Part I
- Course Introduction and Motivation: Part II
- Basic Operation of a Phase Locked Loop
- Simple Implementation of a Phase Locked Loop
- Input-Output Characteristics of Basic PLL Blocks
- Time Domain Analysis of a Simple PLL
Week 2
- Time Domain Versus Small Signal Analysis of a Simple PLL
- Type and Order of PLL
- Small Signal Analysis of Type-I/II/III PLLs for Phase Step, Frequency Step and Frequency Ramp
- Frequency Acquisition Range for PLLs
- Frequency Acquisition in Type-I PLLs
- Frequency Acquisition Limits in Type-I PLLs
Week 3
- Frequency Acquisition in Type-II PLLs
- Frequency Acquisition Ranges in Type-II PLLs with Ideal and Non-Ideal Integrator
- Frequency Domain Insight in Frequency Acquisition for Type-II PLLs
- Introduction to Clock Multipliers
- Analog Phase Error Detectors: Part I
- Analog Phase Error Detectors: Part II
Week 4
- Digital Phase Error Detectors: Part I
- Digital Phase Error Detectors: Part II
- Range Extension for Phase Error Detectors
- Phase Frequency Detector
- Digital Frequency Detector
- Charge Pump PLL
- Small Signal and Stability Analysis of Type-II Order 2 Charge Pump PLL
Week 5
- Problems in Charge Pump PLL - Dead Zone in PFD
- Problems in Charge Pump PLL - Reference Spur
- Design Procedure for Type-II Order 3 Charge Pump PLL
- Design Procedure for Charge Pump Clock Multiplier
- Sources of Non-Linearities in CP-PLL: Part I
- Sources of Non-Linearities in CP-PLL: Part II
- Noise Analysis in CP-PLL: Part I
Week 6
- Noise Analysis in CP-PLL: Part II
- Noise Analysis in CP-PLL: Part III
- Noise Simulations for CP-PLL Blocks
- Introduction to Oscillators
Week 7
- Low-Swing Ring Oscillator: Part I
- Low-Swing Ring Oscillator: Part II
- Large-Swing Ring Oscillator: Part I
- Large-Swing Ring Oscillator: Part II
Week 8
- Large-Swing Ring Oscillator: Part III
- Large-Swing Ring Oscillator: Part IV
- Large-Swing Ring Oscillator: Part V
- Supply Regulated VCO: Part I
- Supply Regulated VCO: Part II
Week 9
- Supply Regulated VCO: Part III
- Phase Noise in Ring Oscillators
- Circuit-level Design of PFD: Part I
- Circuit-level Design of PFD: Part II
- Circuit-level Design of PFD: Part III
- Circuit-level Design of Charge Pump: Part I
Week 10
- Circuit-level Design of Charge Pump: Part II
- Circuit-level Design of Charge Pump: Part III
- Circuit-level Design of Charge Pump: Part IV
- Circuit-level Design of Charge Pump: Part V
- Circuit-level Design of Charge Pump: Part VI
- Circuit-level Design of Clock Frequency Divider
Week 11
- Techniques for Wide Frequency Range Clock Multiplier
- Introduction to Digital PLL
- Design of Time-to-Digital Converter
- Small Signal Analysis of Digital PLL
Week 12
Syllabus and materials
At NPTEL, as the course publishes them.
Credits and licence
- Institution
- IIT Madras
- Department
- Electrical Engineering
- Teacher
- Prof. Saurabh Saxena
- Level
- Undergraduate
- Language
- English
- Subjects
- Engineering
- Source
- NPTEL
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- NPTEL gives no rating. Invisible Network shows it to Tweens profiles and older, judged from what the source says about it. How courses are placed
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