Lecture 22 of 65Week 4
Phase Frequency Detector
Prof. Saurabh Saxena · IIT Madras
Credits and licence
- From
- Phase-locked loops, IIT Madras (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- Tweens profiles and older. How courses are placed
All the lectures
- Course Introduction and Motivation: Part I
- Course Introduction and Motivation: Part II
- Basic Operation of a Phase Locked Loop
- Simple Implementation of a Phase Locked Loop
- Input-Output Characteristics of Basic PLL Blocks
- Time Domain Analysis of a Simple PLL
- Time Domain Versus Small Signal Analysis of a Simple PLL
- Type and Order of PLL
- Small Signal Analysis of Type-I/II/III PLLs for Phase Step, Frequency Step and Frequency Ramp
- Frequency Acquisition Range for PLLs
- Frequency Acquisition in Type-I PLLs
- Frequency Acquisition Limits in Type-I PLLs
- Frequency Acquisition in Type-II PLLs
- Frequency Acquisition Ranges in Type-II PLLs with Ideal and Non-Ideal Integrator
- Frequency Domain Insight in Frequency Acquisition for Type-II PLLs
- Introduction to Clock Multipliers
- Analog Phase Error Detectors: Part I
- Analog Phase Error Detectors: Part II
- Digital Phase Error Detectors: Part I
- Digital Phase Error Detectors: Part II
- Range Extension for Phase Error Detectors
- Phase Frequency Detector
- Digital Frequency Detector
- Charge Pump PLL
- Small Signal and Stability Analysis of Type-II Order 2 Charge Pump PLL
- Problems in Charge Pump PLL - Dead Zone in PFD
- Problems in Charge Pump PLL - Reference Spur
- Design Procedure for Type-II Order 3 Charge Pump PLL
- Design Procedure for Charge Pump Clock Multiplier
- Sources of Non-Linearities in CP-PLL: Part I
- Sources of Non-Linearities in CP-PLL: Part II
- Noise Analysis in CP-PLL: Part I
- Noise Analysis in CP-PLL: Part II
- Noise Analysis in CP-PLL: Part III
- Noise Simulations for CP-PLL Blocks
- Introduction to Oscillators
- Low-Swing Ring Oscillator: Part I
- Low-Swing Ring Oscillator: Part II
- Large-Swing Ring Oscillator: Part I
- Large-Swing Ring Oscillator: Part II
- Large-Swing Ring Oscillator: Part III
- Large-Swing Ring Oscillator: Part IV
- Large-Swing Ring Oscillator: Part V
- Supply Regulated VCO: Part I
- Supply Regulated VCO: Part II
- Supply Regulated VCO: Part III
- Phase Noise in Ring Oscillators
- Circuit-level Design of PFD: Part I
- Circuit-level Design of PFD: Part II
- Circuit-level Design of PFD: Part III
- Circuit-level Design of Charge Pump: Part I
- Circuit-level Design of Charge Pump: Part II
- Circuit-level Design of Charge Pump: Part III
- Circuit-level Design of Charge Pump: Part IV
- Circuit-level Design of Charge Pump: Part V
- Circuit-level Design of Charge Pump: Part VI
- Circuit-level Design of Clock Frequency Divider
- Techniques for Wide Frequency Range Clock Multiplier
- Introduction to Digital PLL
- Design of Time-to-Digital Converter
- Small Signal Analysis of Digital PLL
- Noise Analysis in Digital PLL
- Analog/Digital Hybrid PLL: Part I
- Analog/Digital Hybrid PLL: Part II
- Course Summary