Learn · Digital System Design

Lecture 49 of 68Week 10

State machine reduction

Prof. Neeraj Goel · IIT Ropar

Credits and licence

From
Digital System Design, IIT Ropar (at NPTEL)
Licence
CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
Attribution
NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge. Coordinated by IIT Madras.
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All the lectures

  1. Introduction Video
  2. Analog vs Digital Video
  3. Binary number system-1 Video
  4. Binary number system-2 Video
  5. Negative number representation-1 Video
  6. Negative number representation-2 Video
  7. Other number systems Video
  8. Floating point number-1 Video
  9. Floating point numbers-2 Video
  10. Floating point numbers-3 Video
  11. Floating point numbers-4 Video
  12. Boolean functions Video
  13. Boolean Algebra Video
  14. SOP and POS Representation Video
  15. Algebraic simplifications Video
  16. Canonical form Video
  17. Boolean minimization using K-Maps Video
  18. More Logic gates Video
  19. Hardware description language:Verilog Video
  20. Verilog simulation demo Video
  21. K-maps Video
  22. Area delay model Video
  23. Multiplexer Video
  24. Four state logic Video
  25. Decoders-1 Video
  26. Decoders-2 Video
  27. Encoders Video
  28. Programmable hardware Video
  29. Ripple carry adder Video
  30. Carry look ahead adder Video
  31. Modeling BUS in Verilog Video
  32. Fast adder:Carry select adder Video
  33. Multiple operand adder Video
  34. Multiplication Video
  35. Introduction to sequential circuits Video
  36. Latches Video
  37. D-Flip-flops Video
  38. More Flip-flops Video
  39. Counters Video
  40. Verilog-Behavior model-1 Video
  41. Verilog-Behavior model-2 Video
  42. Registers-1 Video
  43. Registers-2 Video
  44. Memory Video
  45. Sequential circuit analysis Video
  46. Derivation state graph Video
  47. Sequence detector: Example 1 Video
  48. Sequence detector: Example 2 Video
  49. State machine reduction Video
  50. State encoding Video
  51. Multi-cycle adder design Video
  52. Pipelined adder design Video
  53. Multiplication design Video
  54. Division hardware design Video
  55. Interacting state machines Video
  56. Register Transfer Level design Video
  57. GCD computer at RTL Level Video
  58. RTL Design-Bubble sort Video
  59. RTL Design - Traffic light controller Video
  60. FPGA Video
  61. Xilinx CLB Video
  62. FPGA - Design flow Video
  63. FPGA design demo Video
  64. Introduction to ASIC design flow Part - 1 Video
  65. Introduction to ASIC design flow Part - 2 Video
  66. Future directions Video
  67. Live Session 21-02-2021 Video
  68. Live Session 21-02-2022 Video