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Course10810617768 lectures

Digital System Design

Prof. Neeraj Goel · IIT Ropar

Start with lecture 1 At NPTEL

Lectures

Week 1

  1. Introduction Video
  2. Analog vs Digital Video
  3. Binary number system-1 Video
  4. Binary number system-2 Video
  5. Negative number representation-1 Video
  6. Negative number representation-2 Video

Week 2

  1. Other number systems Video
  2. Floating point number-1 Video
  3. Floating point numbers-2 Video
  4. Floating point numbers-3 Video
  5. Floating point numbers-4 Video

Week 3

  1. Boolean functions Video
  2. Boolean Algebra Video
  3. SOP and POS Representation Video
  4. Algebraic simplifications Video
  5. Canonical form Video
  6. Boolean minimization using K-Maps Video
  7. More Logic gates Video

Week 4

  1. Hardware description language:Verilog Video
  2. Verilog simulation demo Video
  3. K-maps Video
  4. Area delay model Video

Week 5

  1. Multiplexer Video
  2. Four state logic Video
  3. Decoders-1 Video
  4. Decoders-2 Video
  5. Encoders Video
  6. Programmable hardware Video

Week 6

  1. Ripple carry adder Video
  2. Carry look ahead adder Video
  3. Modeling BUS in Verilog Video
  4. Fast adder:Carry select adder Video
  5. Multiple operand adder Video
  6. Multiplication Video

Week 7

  1. Introduction to sequential circuits Video
  2. Latches Video
  3. D-Flip-flops Video
  4. More Flip-flops Video
  5. Counters Video

Week 8

  1. Verilog-Behavior model-1 Video
  2. Verilog-Behavior model-2 Video
  3. Registers-1 Video
  4. Registers-2 Video
  5. Memory Video

Week 9

  1. Sequential circuit analysis Video
  2. Derivation state graph Video
  3. Sequence detector: Example 1 Video
  4. Sequence detector: Example 2 Video

Week 10

  1. State machine reduction Video
  2. State encoding Video
  3. Multi-cycle adder design Video
  4. Pipelined adder design Video
  5. Multiplication design Video
  6. Division hardware design Video
  7. Interacting state machines Video

Week 11

  1. Register Transfer Level design Video
  2. GCD computer at RTL Level Video
  3. RTL Design-Bubble sort Video
  4. RTL Design - Traffic light controller Video

Week 12

  1. FPGA Video
  2. Xilinx CLB Video
  3. FPGA - Design flow Video
  4. FPGA design demo Video
  5. Introduction to ASIC design flow Part - 1 Video
  6. Introduction to ASIC design flow Part - 2 Video
  7. Future directions Video

Live Session

  1. Live Session 21-02-2021 Video
  2. Live Session 21-02-2022 Video

Syllabus and materials

At NPTEL, as the course publishes them.

Credits and licence

Institution
IIT Ropar
Department
Electrical Engineering
Teacher
Prof. Neeraj Goel
Level
Undergraduate
Language
English
Subjects
Engineering
Source
NPTEL
Licence
CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
Attribution
NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge. Coordinated by IIT Madras.
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