Learn · Design and Analysis of VLSI Subsystems
Lecture 83 of 95week-11
11.9 - Static Timing Analysis - Part6
Prof. Madhav Rao · IIIT Bangalore
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- Design and Analysis of VLSI Subsystems, IIIT Bangalore (at NPTEL)
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- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
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- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge. Coordinated by IIT Madras.
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All the lectures
- 1.1 - Understanding Silicon
- 1.2 - Introduction to NMOS
- 1.3 - NMOS Transistor Working
- 1.4 - PMOS Transistor
- 1.5 - MOS Capacitances
- 1.6 - Non Ideal MOS model
- 1.7 - Short channel current model
- 1.8 - Short channel current model analysis
- 2.1 - Channel Length modulation index
- 2.2 - DC characteristics of Inverter
- 2.3 - Transfer characteristics of Inverter
- 2.4 - Skewed Inverter
- 2.5 - Skewed Inverter and threshold voltage
- 2.6 - Equivalent of transistors in series
- 2.7 - Transmission Gate
- 3.1 - Bad CMOS Buffer - Part1
- 3.2 - Bad CMOS Buffer - Part2
- 3.3 - Noise margin characteristics of inverter
- 3.4 - Noise margin parameters
- 3.5 - Introduction to Delay in CMOS
- 3.6 - Transient analysis of CMOS Inverter
- 3.7 - RC approximated delay
- 3.8 - Switching Resistance
- 4.1 - CMOS Inverter approximated to RC Circuit
- 4.2 - Elmore delay
- 4.3 - Delay of FO4 inverter
- 4.4 - Extracting capacitances of 3-Nand gate for delay estimation
- 4.5 - Characterizing Delay of NOR gate
- 4.6 - Linear Delay model
- 4.7 - Logical effort and Parasitic delay
- 5.1 - Logical effort and Parasitic delay for different gates
- 5.2 - Logical effort for short-channel current model
- 5.3 - Ring Oscillator design
- 5.4 - Optimizing Gate Size
- 5.5 - Optimizing Gate Sizes Example
- 5.6 - Optimizing the Stages for an inverter path
- 5.7 - Optimizing the Stages for a General Circuit
- 5.8 - Decoder Design
- 6.1 - Introduction to Combinational Circuit and assymetric gates
- 6.2 - Assymetric Gates analysis
- 6.3 - Assymetric Gates analysis using short-channel current model
- 6.4 - Introduction to Skewed gates
- 6.5 - Skewed gates and best P/N ratio
- 6.6 - vIntroduction to Pseudo NMOS
- 6.7 - Psudeo NMOS gates
- 6.8 - Other Logic Family
- 6.9 - Dynamic Logic and Domino logic
- 7.1 - Domino gates
- 7.2 - Introduction to Stick Diagram
- 7.3 - Stick Diagram for different gates
- 7.4 - Applying Eulers path for stick diagram representations
- 7.5 - Multiplexer design and layout
- 7.6 - Introduction to Interconnects
- 7.7 - Interconnects - RC delay, and Energy
- 8.1 - Introduction to crosstalks in interconnects
- 8.2 - Transient analysis in Crosstalk
- 8.3 - Introduction to Repeaters in Interconnect Engineering
- 8.4 - Repeater Design
- 8.5 - Energy and delay analysis for interconnectwith repeaters
- 8.6 - Repeater Design and Energy-Delay-Product
- 8.7 - Introduction to Power
- 9.1 - Switching Power and Energy Estimation
- 9.2 - Activity factor and estimating dynamic power for a combinational circuit design
- 9.3 - Analyzing Dynamic Power
- 9.4 - Energy estimation through driving factor
- 9.5 - Energy expression in terms of delay
- 9.6 - Voltage Scaling
- 9.7 - DVFS
- 10.1 - Introduction to subthreshold leakage current model
- 10.2 - Subthreshold leakage current and Gate leakage current
- 10.3 - Estimating Static Power
- 10.4 - Introduction to CMOS Latch design
- 10.5 - CMOS Latch Design
- 10.6 - CMOS Latch and flipflop design
- 11.1 - Static Timing Analysis
- 11.2 - Static Timing Analysis - Continued
- 11.3 - Static Timing Analysis - Part2
- 11.4 - Static Timing Analysis - Part2.1
- 11.5 - Static Timing Analysis - Part3
- 11.6 - TPDQ and TPCQ
- 11.7 - Static Timing Analysis - Part4
- 11.8 - Static Timing Analysis - Part5
- 11.9 - Static Timing Analysis - Part6
- 11.10 - SET and CLEAR enabled Latch and Flipflop Design
- 12.1 - 1-bit Adder design
- 12.2 - Adder-Part2
- 12.3 - PG architecture - Part1
- 12.4 - PG architecture - Part2
- 12.5 - Carry Skip Adder
- 12.6 - Carry Look Ahead and Carry Increment Adder
- 12.7 - Other Adder Subsystems
- 12.8 - Approximate Multipliers - Part 1
- 12.9 - Approximate Multipliers - Part 2
- 12.10 - Approximate Adder
- Live Session 26-02-2022