Learn · VLSI Design Verification and test
Lecture 50 of 54Sequential Circuit Testing and Scan Chains and Built In Self Test (BIST)
ATPG for Synchronous Sequential Circuits
Prof. Santhosh biswas, Prof. Jatindra Kumar Deka and Prof. Arnab Sarkar · IIT Guwahati
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- VLSI Design Verification and test, IIT Guwahati (at NPTEL)
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All the lectures
- Introduction Part-1
- Introduction Part-2
- Overview of VLSI Design Flow
- High Level Synthesis Overview Part 1
- High Level Synthesis Overview Part 2
- Scheduling in HLS (Part-1)
- Scheduling in HLS (Part-2)
- Scheduling in HLS (Part-3)
- Scheduling in HLS (Part-4)
- Scheduling in HLS (Part-5)
- Scheduling in HLS (Part-6)
- Scheduling in HLS (Part-7)
- Resource Sharing and Binding in HLS (Part-1)
- Resource Sharing and Binding in HLS (Part-2)
- Resource Sharing and Binding in HLS (Part-3)
- Resource Sharing and Binding in HLS (Part-4)
- Resource Sharing and Binding in HLS (Part-5)
- Resource Sharing and Binding in HLS (Part-6)
- Resource Sharing and Binding in HLS (Part-7)
- Logic Synthesis (Part-1)
- Logic Synthesis (Part-2)
- Logic Synthesis (Part-3)
- Physical Design (Part-1)
- Physical Design (Part-2)
- Physical Design (Part-3)
- Introduction to formal methods for design verification
- Temporal Logic: Introduction and Basic Operations on Temporal Logic
- Syntax and Semantics of CLT
- Syntax and semantics of CTL continued
- Equivalences between CTL Formulas
- Introduction to Model Checking
- Model checking Algorithms
- Model checking Algorithms continued.
- Model Checking with Fairness
- Binary Decision Diagram: Introduction and Construction
- Ordered Binary Decision Diagram (OBDD)
- Operation On OBDD
- OBDD for State Transition Systems E
- Symbolic Model Checking
- Introduction to Digital VLSI Testing
- Functional and Structural Testing
- Fault Equivalence
- Fault Simulation I
- Fault Simulation II
- Fault Simulation III
- Testability Measures (SCOAP)
- Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras
- D-Algorithm I
- D-Algorithm II
- ATPG for Synchronous Sequential Circuits
- Scan Chain based Sequential Circuit Testing I
- Scan Chain based Sequential Circuit Testing II
- BIST I
- BIST II