Course11710312554 lectures

VLSI Design Verification and test

Prof. Santhosh biswas, Prof. Jatindra Kumar Deka and Prof. Arnab Sarkar · IIT Guwahati

Start with lecture 1 At NPTEL

Lectures

Introduction and Overview of VLSI Design

Scheduling in High-Level Synthesis

Resource Sharing and Binding in HLS

Logic Synthesis and Physical Design

Introduction to Verification Techniques

Syntax and semantics of CTL, Equivalences between CTL formulas and Introduction to Model Checking

CTL Model checking Algorithms and Introduction to Binary Decision Diagrams

Binary Decision Diagram and Symbolic model checking

Introduction to Digital Testing

Fault Simulation and Testability Measures

Combinational Circuit Test Pattern Generation

Sequential Circuit Testing and Scan Chains and Built In Self Test (BIST)

Syllabus and materials

At NPTEL, as the course publishes them.

Syllabus

Credits and licence

Institution: IIT Guwahati
Department: Electronics & Communication Engineering
Taught by: Prof. Santhosh biswas, Prof. Jatindra Kumar Deka, Prof. Arnab Sarkar
Level: Undergraduate
Language: English
Subjects: Engineering, Society and politics
Source: NPTEL
Licence: CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
Attribution: NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
Who can watch: NPTEL gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed