Learn · FPGA Based Signal Processing Systems
Lecture 51 of 67Week 11
DFT
Prof. P. Sumathi · IIT Roorkee
Credits and licence
- From
- FPGA Based Signal Processing Systems, IIT Roorkee (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- Tweens profiles and older. How courses are placed
All the lectures
- Introduction to FPGA
- Technology Review: Part 1
- Technology Review: Part 2
- DSP and Integrated Design Suites
- Introduction to Verilog
- Verilog
- Modelling of Digital Circuits
- Modelling of Digital Circuits and Testbench: Part 1
- Modelling of Digital Circuits and Testbench: Part 2
- Testbench, Simulation, and Synthesis
- Structural Modelling of Combinational Logic
- Dataflow Modelling of Combinational Logic
- Behavioral Modelling of Combinational Logic
- Simulation of Combinational Logic Circuits: Part 1
- Simulation of Combinational Logic Circuits: Part 2
- Sequential Logic Circuits: Part 1
- Sequential Logic Circuits: Part 2
- Blocking and Non-Blocking Statements
- Sequential Logic Circuits: Blocking and Non-Blocking Statements, Counters
- Counters and Shift Registers
- Finite State Machines: Part 1
- Finite State Machines: Part 2
- Finite State Machines: Sequence Detector
- FSM: Verilog Modules of Sequence Detector
- FSM: Counters
- Memory Banks
- FSM Modelling Styles
- FSM Modelling Styles and Timing Control
- Timing Controls: Part 1
- Timing Controls: Part 2
- Synthesis of Combinational Logic Circuits
- Synthesis of Sequential Logic Circuits: Part 1
- Synthesis of Sequential Logic Circuits: Part 2
- Synthesis of Sequential Logic Circuits: Part 3
- Synthesis of Finite State Machines
- Arithmetic Basics : Part 1
- Arithmetic Basics : Part 2
- Arithmetic Basics : Part 3
- CORDIC
- Timing Analysis
- Finite Impulse Response Filters: Part-1
- Finite Impulse Response Filters: Part-2
- Finite Impulse Response Filters: Part-3
- Finite Impulse Response Filters: Part-4
- Digital FIR Filters – Verilog Codes
- Infinite Impulse Response Filters: Part 1
- Infinite Impulse Response Filters: Part 2
- Infinite Impulse Response Filters: Part 3
- Digital IIR Filters: Verilog Codes - Part 1
- Digital IIR Filters: Verilog Codes - Part 2
- DFT
- Sliding DFT and its Variants: Part 1
- Sliding DFT and its Variants : Part 2
- DCT
- FFT and DSP Builder Models
- General Discrete-Signal Processing Network : Part 1
- General Discrete-Signal Processing Network : Part 2
- Adaptive Filtering : Part 1
- Adaptive Filtering : Part 2
- Adaptive Filtering : Part 3
- Combinational Logic Circuits: Simulation
- Sequential Logic Circuits: Simulation
- Finite State Machines: Simulation
- Timing Controls: Simulation
- Lab 1 Part 2 : Combinational Logic Circuits: Implementation
- Lab 2: Part 2: Sequential Logic Circuits: Implementation
- Lab 3: Part 2: Finite State Machines: Implementation