Learn · VLSI Design Flow: RTL to GDS
Lecture 49 of 54Week 11
Placement
Prof. Sneh Saurabh · IIIT Delhi
Credits and licence
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- VLSI Design Flow: RTL to GDS, IIIT Delhi (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge. Coordinated by IIT Madras.
- Who can watch
- Tweens profiles and older. How courses are placed
All the lectures
- Basic Concepts of Integrated Circuit - I
- Basic Concepts of Integrated Circuit - II
- Overview of VLSI Design Flow - I
- Overview of VLSI Design Flow - II
- Tutorial 1
- Overview of VLSI Design Flow - III
- Overview of VLSI Design Flow - IV
- Overview of VLSI Design Flow - V
- Overview of VLSI Design Flow - VI
- Introduction to TCL
- Hardware Modeling: Introduction to Verilog-I
- Hardware Modeling: Introduction to Verilog-II
- Functional Verification using Simulation
- High-level synthesis using Bambu - Tutorial 3
- RTL Synthesis- Part I
- RTL Synthesis- Part II
- Logic Optimization: Part I
- Simulation-based Verification using Icarus
- Logic Optimization: Part II
- Logic Optimization: Part III
- Formal Verification-I
- Logic Synthesis using Yosys
- Formal Verification-II
- Formal Verification-III
- Formal Verification-IV
- Technology Library
- Logic Optimization using Yosys
- Static Timing Analysis- I
- Static Timing Analysis- II
- Static Timing Analysis- III
- Static Timing Analysis using OpenSTA
- Constraints I
- Constraints II
- Technology Mapping
- Timing-driven Optimization
- Technology Library and Constraints
- Power Analysis
- Power Optimization
- Basic Concepts of DFT
- Scan Design Flow
- Power Analysis using OpenSTA
- Automatic Test Pattern Generation (ATPG)
- Built-in Self Test (BIST)
- Basic Concepts for Physical Design - I
- Basic Concepts for Physical Design - II
- Installation of OpenRoad
- Chip Planning - I
- Chip Planning - II
- Placement
- Chip Planning and Placement
- Clock Tree Synthesis (CTS)
- Routing
- Post-layout Verification and Signoff
- Clock Tree Synthesis (CTS) and Routing