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VLSI Design Flow: RTL to GDS

Prof. Sneh Saurabh · IIIT Delhi

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About

This course covers the entire RTL to GDS VLSI design flow, going through various stages of logic synthesis, verification, physical design, and testing. Besides covering the fundamentals of various design tasks, this course will develop skills in modern chip design with the help of activities and demonstrations on freely available CAD tools. This course will enhance the employability of the students and will make them ready to undertake careers in the semiconductor industry.

Prerequisites: Basic Course on Digital Circuits (typically taught in the first/second year of UG Program)

Lectures

Week 1

  1. Basic Concepts of Integrated Circuit - I YouTube
  2. Basic Concepts of Integrated Circuit - II YouTube
  3. Overview of VLSI Design Flow - I YouTube
  4. Overview of VLSI Design Flow - II YouTube
  5. Tutorial 1 YouTube

Week 2

  1. Overview of VLSI Design Flow - III YouTube
  2. Overview of VLSI Design Flow - IV YouTube
  3. Overview of VLSI Design Flow - V YouTube
  4. Overview of VLSI Design Flow - VI YouTube
  5. Introduction to TCL YouTube

Week 3

  1. Hardware Modeling: Introduction to Verilog-I YouTube
  2. Hardware Modeling: Introduction to Verilog-II YouTube
  3. Functional Verification using Simulation YouTube
  4. High-level synthesis using Bambu - Tutorial 3 YouTube

Week 4

  1. RTL Synthesis- Part I YouTube
  2. RTL Synthesis- Part II YouTube
  3. Logic Optimization: Part I YouTube
  4. Simulation-based Verification using Icarus YouTube

Week 5

  1. Logic Optimization: Part II YouTube
  2. Logic Optimization: Part III YouTube
  3. Formal Verification-I YouTube
  4. Logic Synthesis using Yosys YouTube

Week 6

  1. Formal Verification-II YouTube
  2. Formal Verification-III YouTube
  3. Formal Verification-IV YouTube
  4. Technology Library YouTube
  5. Logic Optimization using Yosys YouTube

Week 7

  1. Static Timing Analysis- I YouTube
  2. Static Timing Analysis- II YouTube
  3. Static Timing Analysis- III YouTube
  4. Static Timing Analysis using OpenSTA YouTube

Week 8

  1. Constraints I YouTube
  2. Constraints II YouTube
  3. Technology Mapping YouTube
  4. Timing-driven Optimization YouTube
  5. Technology Library and Constraints YouTube

Week 9

  1. Power Analysis YouTube
  2. Power Optimization YouTube
  3. Basic Concepts of DFT YouTube
  4. Scan Design Flow YouTube
  5. Power Analysis using OpenSTA YouTube

Week 10

  1. Automatic Test Pattern Generation (ATPG) YouTube
  2. Built-in Self Test (BIST) YouTube
  3. Basic Concepts for Physical Design - I YouTube
  4. Basic Concepts for Physical Design - II YouTube
  5. Installation of OpenRoad YouTube

Week 11

  1. Chip Planning - I YouTube
  2. Chip Planning - II YouTube
  3. Placement YouTube
  4. Chip Planning and Placement YouTube

Week 12

  1. Clock Tree Synthesis (CTS) YouTube
  2. Routing YouTube
  3. Post-layout Verification and Signoff YouTube
  4. Clock Tree Synthesis (CTS) and Routing YouTube

Syllabus and materials

At NPTEL, as the course publishes them.

Credits and licence

Institution
IIIT Delhi
Department
Electrical Engineering
Teacher
Prof. Sneh Saurabh
Level
Undergraduate
Language
English
Subjects
Engineering
Source
NPTEL
Licence
CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
Attribution
NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge. Coordinated by IIT Madras.
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