Learn · Mapping Signal Processing Algorithms to Architectures
Lecture 57 of 105Week 5
DEMO: Analyze FFT implementation
Prof. Nitin Chandrachoodan · IIT Madras
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- Mapping Signal Processing Algorithms to Architectures, IIT Madras (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
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All the lectures
- Introduction: Objectives and Pre-requisites
- Review of digital logic
- Timing and Power in digital circuits
- Implementation Costs and Metrics
- Example: Audio processing
- Example: AlexNet
- Architecture cost components
- Examples of Architectures
- Multi-objective Optimization
- Number representation
- Scientific notation and Floating point
- Basic FIR filter
- Serial FIR filter architectures
- Simple programmable architecture
- Block diagrams and SFGs
- Dataflow Graphs
- Iteration period
- FIR filter iteration period
- IIR filter iteration period
- Computation Model
- Constraint analysis for IPB computation
- Motivational examples for IPB
- General IPB computation
- Sample period calculation
- Parallel architecture
- Odd-even register reuse
- Power consumption
- Pipelining
- Pipelining FIR filter
- Time-invariant systems
- Valid pipelining examples
- Feedforward cutsets
- Balanced pipeline
- Retiming basic concept
- Example and uses of retiming
- Resource sharing: adder example
- Changing iteration period
- Hardware assumptions and constraint analysis
- Mathematical formulation
- Examples with formulation
- Example: Biquad filter
- Hardware architecture
- Review biquad folding sets
- Complete biquad hardware
- DEMO: FFT in Vivado HLS
- DEMO: FFT synthesis
- Obtaining a folding schedule
- ASAP schedule
- Utilization Efficiency
- ALAP schedule
- Iteration period bound and scheduling
- Retiming for scheduling
- Blocked schedules
- Overlapped schedules
- Improved blocked schedule
- Allocation, Binding and Scheduling
- DEMO: Analyze FFT implementation
- DEMO: FFT interface
- Scheduling: problem formulation
- Example: differential equation solver
- Heuristic approaches to scheduling
- Mathematical formulation
- ILP formulation
- List scheduling
- Hardware model
- Force Directed Scheduling
- DEMO: HLS on FFT
- DEMO: FFT Simulation and Optimization
- DEMO: CPU interfacing
- Software Compilation
- Optimization Examples
- Loop optimizations 1
- Loop optimizations 2
- Loop optimizations 3
- Software pipelining 1
- Software pipelining 2
- FFT Optimization
- Demo: Vivado setup
- Background: CPUs and FPGAs
- Demo: Vivado HLS FFT IP Export
- Demo: Vivado ILA and VIO on hardware
- Demo: FFT on FPGA board
- Demo: Simulating SoC and SDK
- Background: Understanding ELF files
- On-chip communication basics
- Many-to-Many communication
- AXI bus handshaking
- AXI bus (contd)
- Demo: Microblaze processor on FPGA
- Demo: Performance counter AXI peripheral
- Demo: HW accelerator for FPGA
- DMA and arbitration
- Network-on-chip basics
- NoC - topologies and metrics
- NoC - routing
- NoC - switching and flow control
- Systolic Arrays - Background
- Systolic Arrays - Examples
- CORDIC algorithm
- Parallel implementation of FIR filters
- Unfolding Transformation
- Lookahead Transformation
- Introduction to GPUs and Matrix multiplication
- Live Session 09-08-2019
- Live Session 27-08-2019