Learn · System Design through Verilog
Lecture 14 of 27Week 5: Dataflow and behavioral modeling
Lec 14: Basics of dataflow modeling
Prof. Shaik Rafi Ahamed · IIT Guwahati
Credits and licence
- From
- System Design through Verilog, IIT Guwahati (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
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All the lectures
- Lec 1: Verilog Operators and Modules
- Lec 2: Verilog Ports, Data types and Assignments
- Lec 3: Basics of gate level modeling
- Lec 4: Half adder, full adder and ripple carry adder
- Lec 5: Parallel adder/subtractor
- Lec 6: Multiplier and comparator
- Lec 7: Decoder, encoder and multiplexer
- Lec 8: Demultiplexer, read only memory
- Lec 9: Review of flip-flops
- Lec 10: Verilog modeling of flip-flops
- Lec 11: Modeling of CMOS gates and Boolean functions
- Lec 12: Modeling using transmission gates, CMOS delay times
- Lec 13: Signal strengths
- Lec 14: Basics of dataflow modeling
- Lec 15: Examples of dataflow modeling
- Lec 16: Basics of behavioral modeling
- Lec 17: Examples of behavioral modeling
- Lec 18: Verilog modeling of counters
- Lec 19: Verilog modeling of sequence detector
- Lec 20: Verilog modeling FSMs and shift registers
- Lec 21: Combinational circuit examples
- Lec 22: Sequential circuit examples
- Lec 23: Arithmetic and Logic Unit (ALU)
- Lec 24: Static RAM and Braun Multiplier
- Lec 25: FIR filter implementation
- Lec 26: Baugh-Wooley signed multiplier architecture
- Lec 27: IIR filter implementation