Learn · NPTEL

Course10810317927 lectures

System Design through Verilog

Prof. Shaik Rafi Ahamed · IIT Guwahati

Start with lecture 1 At NPTEL

About

A comprehensive resource on Verilog HDL for beginners and experts large and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. Design Through Verilog HDL affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool.

INTENDED AUDIENCE : Undergraduate, post graduate students, faculty and industry people

PREREQUISITES : Digital Circuits

INDUSTRIES SUPPORT : Cadence/Mentor graphics

Lectures

Week 1: Introduction to Verilog

  1. Lec 1: Verilog Operators and Modules YouTube
  2. Lec 2: Verilog Ports, Data types and Assignments YouTube
  3. Lec 3: Basics of gate level modeling YouTube

Week 2 : Gate level modeling-I

  1. Lec 4: Half adder, full adder and ripple carry adder YouTube
  2. Lec 5: Parallel adder/subtractor YouTube
  3. Lec 6: Multiplier and comparator YouTube

Week 3: Gate level modeling-II

  1. Lec 7: Decoder, encoder and multiplexer YouTube
  2. Lec 8: Demultiplexer, read only memory YouTube
  3. Lec 9: Review of flip-flops YouTube
  4. Lec 10: Verilog modeling of flip-flops YouTube

Week 4: Switch level modeling

  1. Lec 11: Modeling of CMOS gates and Boolean functions YouTube
  2. Lec 12: Modeling using transmission gates, CMOS delay times YouTube
  3. Lec 13: Signal strengths YouTube

Week 5: Dataflow and behavioral modeling

  1. Lec 14: Basics of dataflow modeling YouTube
  2. Lec 15: Examples of dataflow modeling YouTube
  3. Lec 16: Basics of behavioral modeling YouTube
  4. Lec 17: Examples of behavioral modeling YouTube

Week 6: Behavioral modeling of sequential circuits

  1. Lec 18: Verilog modeling of counters YouTube
  2. Lec 19: Verilog modeling of sequence detector YouTube
  3. Lec 20: Verilog modeling FSMs and shift registers YouTube

Week 7: Test benches

  1. Lec 21: Combinational circuit examples YouTube
  2. Lec 22: Sequential circuit examples YouTube
  3. Lec 23: Arithmetic and Logic Unit (ALU) YouTube
  4. Lec 24: Static RAM and Braun Multiplier YouTube

Week 8: Case studies

  1. Lec 25: FIR filter implementation YouTube
  2. Lec 26: Baugh-Wooley signed multiplier architecture YouTube
  3. Lec 27: IIR filter implementation YouTube

Syllabus and materials

At NPTEL, as the course publishes them.

Credits and licence

Institution
IIT Guwahati
Department
Electrical Engineering
Teacher
Prof. Shaik Rafi Ahamed
Level
Undergraduate
Language
English
Subjects
Engineering
Source
NPTEL
Licence
CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
Attribution
NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
Who can watch
NPTEL gives no rating. Invisible Network shows it to Tweens profiles and older, judged from what the source says about it. How courses are placed