Learn · Optimization Techniques for Digital VLSI Design
Lecture 11 of 24Logic Synthesis and Physical Synthesis
Overview of FPGA Technology Mapping
Prof. Chandan Karfa and Prof. Santosh Biswas · IIT Guwahati
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- Optimization Techniques for Digital VLSI Design, IIT Guwahati (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
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All the lectures
- Introduction to Digital VLSI Design Flow
- High-level Synthesis (HLS) flow with an example
- Automation of High-level Synthesis Steps
- Impact of Coding Style on HLS Results
- Impact of Compiler Optimizations on HLS Results
- RTL Optimizations for Timing
- Retiming
- RTL Optimizations for Area
- RTL Optimizations for Power
- High Level Synthesis: Introduction to Logic Synthesis
- Overview of FPGA Technology Mapping
- Introduction to Physical Synthesis
- Introduction to Digital VLSI Testing-I
- Introduction to Digital VLSI Testing-II
- Optimization Techniques for ATPG
- Optimization Techniques for ATPG [Part II]
- Optimization Techniques for Design for Testability
- High-level fault modeling and RTL level Testing
- LTL/CTL based Verification
- Verification of Large Scale Systems
- BDD based verification
- Verification: ADD based verification, HDD based verification
- Verification: Symbolic Model Checking
- Verification: Bounded Model Checking