Course10810310824 lectures
Optimization Techniques for Digital VLSI Design
Prof. Chandan Karfa and Prof. Santosh Biswas · IIT Guwahati
Lectures
Introduction and High-level Synthesis
- Introduction to Digital VLSI Design Flow
- High-level Synthesis (HLS) flow with an example
- Automation of High-level Synthesis Steps
Optimizations for HLS and RTL Optimizations
- Impact of Coding Style on HLS Results
- Impact of Compiler Optimizations on HLS Results
- RTL Optimizations for Timing
RTL Optimizations
Logic Synthesis and Physical Synthesis
- High Level Synthesis: Introduction to Logic Synthesis
- Overview of FPGA Technology Mapping
- Introduction to Physical Synthesis
VLSI Testing 1
- Introduction to Digital VLSI Testing-I
- Introduction to Digital VLSI Testing-II
- Optimization Techniques for ATPG
VLSI Testing 2
- Optimization Techniques for ATPG [Part II]
- Optimization Techniques for Design for Testability
- High-level fault modeling and RTL level Testing
Verification 1
Verification 2
Syllabus and materials
At NPTEL, as the course publishes them.
Credits and licence
- Institution
- IIT Guwahati
- Department
- Electrical Engineering
- Taught by
- Prof. Chandan Karfa, Prof. Santosh Biswas
- Level
- Undergraduate
- Language
- English
- Subjects
- Engineering
- Source
- NPTEL
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- NPTEL gives no rating. Invisible Network shows it to Tweens profiles and older, judged from what the source says about it. How courses are placed
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