Learn · Hardware Modeling using Verilog
Lecture 36 of 41Week 7
Lecture 36 : SWITCH LEVEL MODELING (PART 2)
Prof. Indranil Sengupta · IIT Kharagpur
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- Hardware Modeling using Verilog, IIT Kharagpur (at NPTEL)
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- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
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All the lectures
- Lecture 1: Introduction
- Lecture 2 : Design Representation
- Lecture 3 : Getting Started with Verilog
- Lecture 4: VLSI Design Styles (Part 1)
- Lecture 5 : VLSI Design Styles (Part 2)
- Lecture 6: VERILOG LANGUAGE FEATURES (PART 1)
- Lecture 7: VERILOG LANGUAGE FEATURES (PART 2)
- Lecture 8: VERILOG LANGUAGE FEATURES (PART 3)
- Lecture 9: VERILOG OPERATORS
- Lecture 10: VERILOG MODELING EXAMPLES
- Lecture 11: VERILOG MODELING EXAMPLES (Contd)
- Lecture 12: VERILOG DESCRIPTION STYLES
- Lecture 13: PROCEDURAL ASSIGNMENT
- Lecture 14: PROCEDURAL ASSIGNMENT (Contd.)
- Lecture 15: PROCEDURAL ASSIGNMENT (EXAMPLES)
- Lecture 16: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 1)
- Lecture 17: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)
- Lecture 18: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 3)
- Lecture 19: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 4)
- Lecture 20: USER DEFINED PRIMITIVES
- Lecture 21 : VERILOG TEST BENCH
- Lecture 22 : WRITING VERILOG TEST BENCHES
- Lecture 23 : MODELING FINITE STATE MACHINES
- Lecture 24 : MODELING FINITE STATE MACHINES (Contd.)
- Lecture 25 : DATAPATH AND CONTROLLER DESIGN (PART 1)
- Lecture 26 : DATAPATH AND CONTROLLER DESIGN (PART 2)
- Lecture 27 : DATAPATH AND CONTROLLER DESIGN (PART 3)
- Lecture 28 : SYNTHESIZABLE VERILOG
- Lecture 29 : SOME RECOMMENDED PRACTICES
- Lecture 30 : MODELING MEMORY
- Lecture 31 : MODELING REGISTER BANKS
- Lecture 32 : BASIC PIPELINING CONCEPTS
- Lecture 33 : PIPELINE MODELING (PART 1)
- Lecture 34 : PIPELINE MODELING (PART 2)
- Lecture 35 : SWITCH LEVEL MODELING (PART 1)
- Lecture 36 : SWITCH LEVEL MODELING (PART 2)
- Lecture 37 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 1)
- Lecture 38 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 2)
- Lecture 39 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 3)
- Lecture 40 : VERILOG MODELING OF THE PROCESSOR (PART 1)
- Lecture 41 : VERILOG MODELING OF THE PROCESSOR (PART 2)