Learn · NPTEL

Course10610516541 lectures

Hardware Modeling using Verilog

Prof. Indranil Sengupta · IIT Kharagpur

Start with lecture 1 At NPTEL

About

The course will introduce the participants to the Verilog hardware description language. It will help them to learn various digital circuit modeling issues using Verilog, writing test benches, and some case studies.

Intended audience: Computer Science and Engineering ; Electronics and Communication Engineering ; Electrical Engineering

Prerequisites: Basic concepts in digital circuit design ; Familiarity with a programming language like C or C++

Lectures

Week 1

  1. Lecture 1: Introduction YouTube
  2. Lecture 2 : Design Representation YouTube
  3. Lecture 3 : Getting Started with Verilog YouTube
  4. Lecture 4: VLSI Design Styles (Part 1) YouTube
  5. Lecture 5 : VLSI Design Styles (Part 2) YouTube

Week 2

  1. Lecture 6: VERILOG LANGUAGE FEATURES (PART 1) YouTube
  2. Lecture 7: VERILOG LANGUAGE FEATURES (PART 2) YouTube
  3. Lecture 8: VERILOG LANGUAGE FEATURES (PART 3) YouTube
  4. Lecture 9: VERILOG OPERATORS YouTube
  5. Lecture 10: VERILOG MODELING EXAMPLES YouTube
  6. Lecture 11: VERILOG MODELING EXAMPLES (Contd) YouTube

Week 3

  1. Lecture 12: VERILOG DESCRIPTION STYLES YouTube
  2. Lecture 13: PROCEDURAL ASSIGNMENT YouTube
  3. Lecture 14: PROCEDURAL ASSIGNMENT (Contd.) YouTube
  4. Lecture 15: PROCEDURAL ASSIGNMENT (EXAMPLES) YouTube

Week 4

  1. Lecture 16: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 1) YouTube
  2. Lecture 17: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2) YouTube
  3. Lecture 18: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 3) YouTube
  4. Lecture 19: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 4) YouTube
  5. Lecture 20: USER DEFINED PRIMITIVES YouTube

Week 5

  1. Lecture 21 : VERILOG TEST BENCH YouTube
  2. Lecture 22 : WRITING VERILOG TEST BENCHES YouTube
  3. Lecture 23 : MODELING FINITE STATE MACHINES YouTube
  4. Lecture 24 : MODELING FINITE STATE MACHINES (Contd.) YouTube

Week 6

  1. Lecture 25 : DATAPATH AND CONTROLLER DESIGN (PART 1) YouTube
  2. Lecture 26 : DATAPATH AND CONTROLLER DESIGN (PART 2) YouTube
  3. Lecture 27 : DATAPATH AND CONTROLLER DESIGN (PART 3) YouTube
  4. Lecture 28 : SYNTHESIZABLE VERILOG YouTube
  5. Lecture 29 : SOME RECOMMENDED PRACTICES YouTube

Week 7

  1. Lecture 30 : MODELING MEMORY YouTube
  2. Lecture 31 : MODELING REGISTER BANKS YouTube
  3. Lecture 32 : BASIC PIPELINING CONCEPTS YouTube
  4. Lecture 33 : PIPELINE MODELING (PART 1) YouTube
  5. Lecture 34 : PIPELINE MODELING (PART 2) YouTube
  6. Lecture 35 : SWITCH LEVEL MODELING (PART 1) YouTube
  7. Lecture 36 : SWITCH LEVEL MODELING (PART 2) YouTube

Week 8

  1. Lecture 37 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 1) YouTube
  2. Lecture 38 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 2) YouTube
  3. Lecture 39 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 3) YouTube
  4. Lecture 40 : VERILOG MODELING OF THE PROCESSOR (PART 1) YouTube
  5. Lecture 41 : VERILOG MODELING OF THE PROCESSOR (PART 2) YouTube

Syllabus and materials

At NPTEL, as the course publishes them.

Credits and licence

Institution
IIT Kharagpur
Department
Computer Science and Engineering
Teacher
Prof. Indranil Sengupta
Level
Undergraduate
Language
English
Subjects
Computer science, Engineering
Source
NPTEL
Licence
CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
Attribution
NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
Who can watch
NPTEL gives no rating. Invisible Network shows it to Tweens profiles and older, judged from what the source says about it. How courses are placed