Learn · Parallel Computer Architecture

Lecture 13 of 71Week 3: Memory Hierarchy

Lec 13: Memory hierarchy questions (1)

Prof. Hemangee K. Kapoor · IIT Guwahati

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Parallel Computer Architecture, IIT Guwahati (at NPTEL)
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CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
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All the lectures

  1. Lec 1: Why do we need parallel architecture ? Video
  2. Lec 2: Multicore Revolution Video
  3. Lec 3: What is Parallel Architecture? Video
  4. Lec 4: Performance and Benchmarking Video
  5. Lec 5: Reporting Results Video
  6. Lec 6: Some Laws Video
  7. Lec 7: A shift from sequential to parallel Video
  8. Lec 8: Programming Models Video
  9. Lec 9: Shared Memory Paradigm Video
  10. Lec 10: Message Passing Paradigm Video
  11. Lec 11: Examples Video
  12. Lec 12: Cache Basics Video
  13. Lec 13: Memory hierarchy questions (1) Video
  14. Lec 14: Memory hierarchy questions (2) Video
  15. Lec 15: Six basic cache optimisations (1) Video
  16. Lec 16: Six basic cache optimisations (2) Video
  17. Lec 17: Virtual Memory (1) Video
  18. Lec 18: Virtual Memory (2) Video
  19. Lec 19: Cache Coherence Problem Video
  20. Lec 20: Concept of Serialisation Video
  21. Lec 21: Coherence related Conditions Video
  22. Lec 22: Types of Coherence Protocols (1) Video
  23. Lec 23: Types of Coherence Protocols (2) Video
  24. Lec 24: VI Protocol Video
  25. Lec 25: 3 state: MSI Protocol Video
  26. Lec 26: MESI Protocol Video
  27. Lec 27: Dragon Protocol Video
  28. Lec 28: Coherence misses Video
  29. Lec 29: Coherence misses example Video
  30. Lec 30: Correctness Requirements Video
  31. Lec 31: Single-Level caches with an Atomic Bus (1) Video
  32. Lec 32: Single-Level caches with an Atomic Bus (2) Video
  33. Lec 33: Multi-Level caches with an Atomic Bus (1) Video
  34. Lec 34: Multi-Level caches with an Atomic Bus (2) Video
  35. Lec 35: Split transaction Bus Video
  36. Lec 36: Phases in Split Transaction Bus Video
  37. Lec 37: Request table and Organization Video
  38. Lec 38: Path of a Cache Miss Video
  39. Lec 39: Multi-Level cache + Split transaction Bus Video
  40. Lec 40: Introduction to Directory Cache Coherence Video
  41. Lec 41: Basic Operation of a Directory Video
  42. Lec 42: Directory Organisations Video
  43. Lec 43: Directory Overhead Optimisations Video
  44. Lec 44: Directory Protocol optimisations Video
  45. Lec 45:Proving Correctness (1) Video
  46. Lec 46: Proving Correctness (2) Video
  47. Lec 47: SGI Origin Architecture Video
  48. Lec 48: Working of protocol Video
  49. Lec 49: Correctness Issues Video
  50. Lec 50: Sequent NUMA-Q Architecture Video
  51. Lec 51: Working of protocol(1) Video
  52. Lec 52: Working of protocol (2) Video
  53. Lec 53: Correctness and Protocol Interaction Video
  54. Lec 54: Sequential Consistency Video
  55. Lec 55: Implications of Sequential Consistency Video
  56. Lec 56: Relaxed Consistency Models (1) Video
  57. Lec 57: Relaxed Consistency Models (2) Video
  58. Lec 58: Relaxing all Orders Video
  59. Lec 59: Uninterruptible Instructions Video
  60. Lec 60: Implementation of atomic instructions Video
  61. Lec70: Other synchronisation options Video
  62. Lec 71: Interconnect Overview Video
  63. Lec 72: Topologies Video
  64. Lec 73: Routing Video
  65. Lec 74: Flow Control Video
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  67. Live Session 14-03-2024 Video
  68. Live Session 01-04-2024 Video
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