Learn · Digital Design with Verilog

Lecture 34 of 47Week 10 : Optimization

Lec 34: FSM State Optimization using Row Matching and Partitioning Methods

Prof. Chandan Karfa and Prof. Aryabartta Sahu · IIT Guwahati

Credits and licence

From
Digital Design with Verilog, IIT Guwahati (at NPTEL)
Licence
CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
Attribution
NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
Who can watch
Tweens profiles and older. How courses are placed

All the lectures

  1. Lec 1: Introduction to Digital Design with Verilog Video
  2. Lec 2: Switching Algebra Video
  3. Lec 3: Canonical Forms of Switching Functions Video
  4. Lec 4: Number Systems Video
  5. Lec 5: Binary Arithmetic Video
  6. Lec 6: Binary Codes Video
  7. Lec 7: Error Detection and Corrections Codes Video
  8. Lec 8: Minimization of Switching functions-Karnaugh Map Video
  9. Lec 9: Karnaugh Map Video
  10. Lec 10: Minimization of Switching functions-Properties Video
  11. Lec 11: Quine-McCluskey Method Video
  12. Lec 12: Quine-McCluskey Method-Prime Implication Chart Video
  13. Lec 13: ESPRESSO-Heuristic Based Switching Function Minimization Video
  14. Lec 14: Multi-level Logic Minimization Video
  15. Lec 15: Multi-level Logic Minimization-Kernels Extraction Video
  16. Lec 16: Digital Circuits Modelling using Verilog Video
  17. Lec 17: Modelling Techniques in Verilog Video
  18. Lec 18: Behavioral Modelling in Verilog Video
  19. Lec 19: Digital System Design using Verilog Video
  20. Lec 20: Testbench in Verilog Video
  21. Lec 21: Code Conversion, Parity Bit Generator Video
  22. Lec 22: Comparator, Multiplexer Video
  23. Lec 23: Encoder, Decoder Video
  24. Lec 24: Ripple Carry Adder, Carry Look ahead Adder Video
  25. Lec 25: Adder/Subtractor Video
  26. Lec 26: BCD Adder, Multiplier Video
  27. Lec 27:Latch/Storage Design Video
  28. Lec 28:Flipflop Design, Characteristics of Flipflop Video
  29. Lec 29:Flipflop, Register and Memory Video
  30. Lec 30: Digital Counter Video
  31. Lec 31: Finite State Machine Design and Implementation with many Examples Video
  32. Lec 32: FSM Completeness and Correctness Video
  33. Lec 33: Sync Counter using FSM, Implementation using different FFs and Comparision of types of FSM Video
  34. Lec 34: FSM State Optimization using Row Matching and Partitioning Methods Video
  35. Lec 35: State Optimization using Implication chart and State Encoding Video
  36. Lec 36: RTL Design, Introduction to ASM (Algorithmic State Machine) Video
  37. Lec 37:RTL/ASM Design Examples and Implementation Video
  38. Lec 38: ASM Data Path Inference and Control Path Generation Video
  39. Lec 39: Sequential Multplier the Classic Example of RTL Design Video
  40. Lec 40: Introduction to FPGA and Design Flow Video
  41. Lec 41: Introduction to Electronic Design Automation Video
  42. Live Session 08-02-2024 Video
  43. Live Session 18-03-2024 Video
  44. Live Session 05-04-2024 Video
  45. Live Session 11-02-2025 Video
  46. Live Session 06-03-2025 Video
  47. Live Session 02-04-2025 Video