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Course10610335847 lectures

Digital Design with Verilog

Prof. Chandan Karfa and Prof. Aryabartta Sahu · IIT Guwahati

Start with lecture 1 At NPTEL

Lectures

Week 1: Introduction to Digital Design and Switching Algebra

  1. Lec 1: Introduction to Digital Design with Verilog Video
  2. Lec 2: Switching Algebra Video
  3. Lec 3: Canonical Forms of Switching Functions Video
  4. Lec 4: Number Systems Video

Week 2 : Number Systems and Binary Codes

  1. Lec 5: Binary Arithmetic Video
  2. Lec 6: Binary Codes Video
  3. Lec 7: Error Detection and Corrections Codes Video

Week 3 : Minimization of Switching functions

  1. Lec 8: Minimization of Switching functions-Karnaugh Map Video
  2. Lec 9: Karnaugh Map Video
  3. Lec 10: Minimization of Switching functions-Properties Video
  4. Lec 11: Quine-McCluskey Method Video

Week 4 : Heuristic Based Logic Optimization and Multi-level Logic Optimization

  1. Lec 12: Quine-McCluskey Method-Prime Implication Chart Video
  2. Lec 13: ESPRESSO-Heuristic Based Switching Function Minimization Video
  3. Lec 14: Multi-level Logic Minimization Video
  4. Lec 15: Multi-level Logic Minimization-Kernels Extraction Video

Week5 - Verilog

  1. Lec 16: Digital Circuits Modelling using Verilog Video
  2. Lec 17: Modelling Techniques in Verilog Video
  3. Lec 18: Behavioral Modelling in Verilog Video
  4. Lec 19: Digital System Design using Verilog Video
  5. Lec 20: Testbench in Verilog Video

Week6: Combinational Logic Design

  1. Lec 21: Code Conversion, Parity Bit Generator Video
  2. Lec 22: Comparator, Multiplexer Video
  3. Lec 23: Encoder, Decoder Video

Week 7- Combinational Logic Design: Part 2

  1. Lec 24: Ripple Carry Adder, Carry Look ahead Adder Video
  2. Lec 25: Adder/Subtractor Video
  3. Lec 26: BCD Adder, Multiplier Video

Week 8: Sequential Circuits

  1. Lec 27:Latch/Storage Design Video
  2. Lec 28:Flipflop Design, Characteristics of Flipflop Video
  3. Lec 29:Flipflop, Register and Memory Video

Week 9: Counter & FSM

  1. Lec 30: Digital Counter Video
  2. Lec 31: Finite State Machine Design and Implementation with many Examples Video
  3. Lec 32: FSM Completeness and Correctness Video

Week 10 : Optimization

  1. Lec 33: Sync Counter using FSM, Implementation using different FFs and Comparision of types of FSM Video
  2. Lec 34: FSM State Optimization using Row Matching and Partitioning Methods Video
  3. Lec 35: State Optimization using Implication chart and State Encoding Video

week_11: RTL Design : ASM

  1. Lec 36: RTL Design, Introduction to ASM (Algorithmic State Machine) Video
  2. Lec 37:RTL/ASM Design Examples and Implementation Video
  3. Lec 38: ASM Data Path Inference and Control Path Generation Video

Week_12 : RTL, and Design Flow for FPGA and ASIC

  1. Lec 39: Sequential Multplier the Classic Example of RTL Design Video
  2. Lec 40: Introduction to FPGA and Design Flow Video
  3. Lec 41: Introduction to Electronic Design Automation Video

Live Session

  1. Live Session 08-02-2024 Video
  2. Live Session 18-03-2024 Video
  3. Live Session 05-04-2024 Video
  4. Live Session 11-02-2025 Video
  5. Live Session 06-03-2025 Video
  6. Live Session 02-04-2025 Video

Syllabus and materials

At NPTEL, as the course publishes them.

Credits and licence

Institution
IIT Guwahati
Department
Computer Science and Engineering
Taught by
Prof. Chandan Karfa, Prof. Aryabartta Sahu
Level
Undergraduate
Language
English
Subjects
Computer science, Engineering
Source
NPTEL
Licence
CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
Attribution
NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
Who can watch
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