Learn · Multi-Core Computer Architecture
Lecture 5 of 49Week 1: Course Introduction & Basic Computer Organization
Lec 5: Performance Evaluation Methods
Prof. John Jose · IIT Guwahati
Credits and licence
- From
- Multi-Core Computer Architecture, IIT Guwahati (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- Tweens profiles and older. How courses are placed
All the lectures
- Lec 1: Introduction and Overview of the Course
- Lec 2: Review of Basic Computer Organization
- Lec 3: Instruction Set and Addressing Modes
- Lec 4: Instruction Encoding
- Lec 5: Performance Evaluation Methods
- Lec 6:Tutorial on Performance Evaluvation
- Lec 6: Introduction to RISC Instruction Pipeline
- Lec 7: Instruction Pipeline Hazards
- Lec 8: Tutorial on Instruction Pipeline and Hazards
- Lec 9: Control Hazards and Branch Prediction
- Lec 10: MIPS Pipeline for Multi-Cycle Operations
- Lec 11: Tutorial on Longer Pipeline and Branch Prediction
- Lec 12: Compiler Techniques to Explore ILP
- Lec 13: Dynamic Scheduling to Explore ILP
- Lec 14: Dynamic Scheduling with Tomasulo’s Algorithm
- Lec 15: Dynamic Scheduling with Speculative Execution
- Lec 16: Tutorial on Static and Dynamic Scheduling
- Lec 17: Advanced Pipelining & Superscalar Processors
- Lec 18: Introduction to GPU architectures
- Lec 19: Case study on GPU architectures
- Lec 20: Tutorial on Superscalar processors and GPU
- Lec 21: Introduction to Cache Memory
- Lec 22: Block Replacement Techniques & Write Strategy
- Lec 23: Design Concepts in Cache Memory
- Lec 24: Optimization Techniques in Cache Memory
- Lec 25: Advanced Cache Optimization Techniques
- Lec 26: Tutorial on Advanced Concepts in Cache Memory -1
- Lec 27: Tutorial on Advanced Concepts in Cache Memory -2
- Lec 28: Cache coherence and memory consistency
- Lec 29: Snooping Based Cache Coherence
- Lec 30: Directory Based Cache Coherence
- Lec 31: Tutorial on Cache Coherence Protocols
- Lec 32: Introduction to DRAM System
- Lec 33: DRAM Controllers & Address Mapping
- Lec 34: Secondary Storage Systems
- Lec 35: Design Concepts in Storage Systems
- Lec 36: Introduction to Tiled Chip Multicore Processors
- Lec 37: Routing Techniques in Network On Chip
- Lec 38: Network On Chip Router Micro-Architecture
- Lec 39: Concepts in Network on Chip
- Lec 40: Energy Efficient Bufferless NoC Routers
- Lec 41: Sidebuffered Deflection Routers
- Lec 42: Concepts in Deflection Routers [T]
- Lec 43: QoS of NoC and Caches in TCMP Systems
- Lec 44: Emerging Trends in Network On Chips
- Lec 45: Domain Specific Accelarators
- Lec 46: Introduction to VEGA Microprocessors (Case Study)
- Lec 47: Concepts in TCMP Systems
- Lec 48: How to Explore Computer Architecture?