Course10610318449 lectures
Multi-Core Computer Architecture
Prof. John Jose · IIT Guwahati
About
The use of mobile gadgets and applications is crucial to maintaining comfort in modern living. These apps are supported by portable electronic devices with powerful microprocessors. We are in the era of multi-core systems where even the simplest of handheld devices like a smart phone houses many processors in a single chip. The core counts are ever increasing from 8 to 10 in smart phones to over 100s in super computers. This course will introduce the students to the world of multi-core computer architectures. With the unprecedented growth of data science, on-chip storage systems and inter-core communication framework are getting equal attention as that of processors. This course will focus on delivering an in-depth exposure in advanced computer architecture starting from the fundamentals of basic computer organization to advanced topics like multicore processors, GPUs, advanced cache memory optimizations, DRAM systems, on chip interconnects and domain specific accelerators. The course concludes with pointers to current research standings and on-going research directions for motivating the students to explore further.
Intended audience: Anyone in CSE and related fields like ECE, EEE, IT etc. with an interest in exploring Computer Architecture.
Prerequisites: Second-year undergraduate or above or any level of postgraduates in Computer Science and related fields (like ECE, EEE, IT etc.). A basic understanding of digital logic, microprocessors, computer organization will be added advantage.
Lectures
Week 1: Course Introduction & Basic Computer Organization
- Lec 1: Introduction and Overview of the Course
- Lec 2: Review of Basic Computer Organization
- Lec 3: Instruction Set and Addressing Modes
- Lec 4: Instruction Encoding
- Lec 5: Performance Evaluation Methods
- Lec 6:Tutorial on Performance Evaluvation
Week 2: Introduction to RISC Instruction Pipeline and Hazards
- Lec 6: Introduction to RISC Instruction Pipeline
- Lec 7: Instruction Pipeline Hazards
- Lec 8: Tutorial on Instruction Pipeline and Hazards
Week 3: Control Hazards and Branch Prediction Techniques
- Lec 9: Control Hazards and Branch Prediction
- Lec 10: MIPS Pipeline for Multi-Cycle Operations
- Lec 11: Tutorial on Longer Pipeline and Branch Prediction
Week 4: Pipeline Scheduling and Speculative Execution
- Lec 12: Compiler Techniques to Explore ILP
- Lec 13: Dynamic Scheduling to Explore ILP
- Lec 14: Dynamic Scheduling with Tomasulo’s Algorithm
- Lec 15: Dynamic Scheduling with Speculative Execution
- Lec 16: Tutorial on Static and Dynamic Scheduling
Week 5: Superscalar Processors and GPU Architectures
- Lec 17: Advanced Pipelining & Superscalar Processors
- Lec 18: Introduction to GPU architectures
- Lec 19: Case study on GPU architectures
- Lec 20: Tutorial on Superscalar processors and GPU
Week 6: Cache Memory Principles
- Lec 21: Introduction to Cache Memory
- Lec 22: Block Replacement Techniques & Write Strategy
- Lec 23: Design Concepts in Cache Memory
Week 7: Cache Memory Optimizations
- Lec 24: Optimization Techniques in Cache Memory
- Lec 25: Advanced Cache Optimization Techniques
- Lec 26: Tutorial on Advanced Concepts in Cache Memory -1
- Lec 27: Tutorial on Advanced Concepts in Cache Memory -2
Week 8: Cache Coherence Protocols
- Lec 28: Cache coherence and memory consistency
- Lec 29: Snooping Based Cache Coherence
- Lec 30: Directory Based Cache Coherence
- Lec 31: Tutorial on Cache Coherence Protocols
Week 9: Primary and Secondary Storage Systems
- Lec 32: Introduction to DRAM System
- Lec 33: DRAM Controllers & Address Mapping
- Lec 34: Secondary Storage Systems
- Lec 35: Design Concepts in Storage Systems
Week 10: Tiled Chip Multi-Core Processors & Network-on-Chip
- Lec 36: Introduction to Tiled Chip Multicore Processors
- Lec 37: Routing Techniques in Network On Chip
- Lec 38: Network On Chip Router Micro-Architecture
- Lec 39: Concepts in Network on Chip
Week 11: Energy Efficient NoCs
- Lec 40: Energy Efficient Bufferless NoC Routers
- Lec 41: Sidebuffered Deflection Routers
- Lec 42: Concepts in Deflection Routers [T]
Week 12: QoS for TCMPs
Syllabus and materials
At NPTEL, as the course publishes them.
Credits and licence
- Institution
- IIT Guwahati
- Department
- Computer Science and Engineering
- Teacher
- Prof. John Jose
- Level
- Undergraduate
- Language
- English
- Subjects
- Computer science, Engineering
- Source
- NPTEL
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- NPTEL gives no rating. Invisible Network shows it to Tweens profiles and older, judged from what the source says about it. How courses are placed