Learn · Multi-Core Computer Architecture - Storage and Interconnects
Lecture 18 of 31Week 5: DRAM Technology
Address Translation Mechanisms
Prof. John Jose · IIT Guwahati
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- Multi-Core Computer Architecture - Storage and Interconnects, IIT Guwahati (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
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All the lectures
- Introduction and Overview of the Course
- Instruction Execution Principles
- Introduction to Instruction Pipeline
- Introduction to Superscalar Pipelines
- Instruction Pipeline & Performance - I
- Instruction Pipeline & Performance - II
- Introduction to Cache Memory
- Block Replacement Techniques & Write Strategy
- gem5 Simulator - An Overview
- Cache Memory
- Basic Cache Optimization Techniques
- gem5 Simulator - Cache Optimisation
- Advanced Cache Optimization Techniques-I
- Advanced Cache Optimization Techniques-II
- Cache Memory Optimizations
- Introduction to DRAM System
- DRAM Controllers & Address Mapping
- Address Translation Mechanisms
- Main Memory Concepts
- Introduction to Tiled Chip Multicore Processors
- Routing Techniques in Network On Chip
- Network On Chip Router Micro-Architecture
- gem5 Simulator - NoC Optimisation
- Energy Efficient Bufferless NoC Routers
- Sidebuffered Deflection Routers
- Concepts in Network on Chip
- QoS of NoC and Caches in TCMP Systems
- Emerging Trends in Network On Chips
- Concepts in TCMP Systems
- Live Session 23-09-2021
- Live Session 10-11-2021