Course10610318331 lectures
Multi-Core Computer Architecture - Storage and Interconnects
Prof. John Jose · IIT Guwahati
Lectures
Week 1: Course Introduction & Pipelined Instruction Execution Principles
- Introduction and Overview of the Course
- Instruction Execution Principles
- Introduction to Instruction Pipeline
- Introduction to Superscalar Pipelines
- Instruction Pipeline & Performance - I
- Instruction Pipeline & Performance - II
Week 2: Cache Memory Design Concepts
- Introduction to Cache Memory
- Block Replacement Techniques & Write Strategy
- gem5 Simulator - An Overview
- Cache Memory
Week 3: Basic Cache Optimizations
Week 4: Advanced Cache Optimizations
- Advanced Cache Optimization Techniques-I
- Advanced Cache Optimization Techniques-II
- Cache Memory Optimizations
Week 5: DRAM Technology
- Introduction to DRAM System
- DRAM Controllers & Address Mapping
- Address Translation Mechanisms
- Main Memory Concepts
Week 6: Tiled Chip Multi-Core Processors & Network-on-Chip
- Introduction to Tiled Chip Multicore Processors
- Routing Techniques in Network On Chip
- Network On Chip Router Micro-Architecture
- gem5 Simulator - NoC Optimisation
Week 7: Network-on-Chip Architectures
Week 8: QoS for TCMPs at Storage and Interconnect Levels
Live Session
Syllabus and materials
At NPTEL, as the course publishes them.
Credits and licence
- Institution
- IIT Guwahati
- Department
- Computer Science and Engineering
- Teacher
- Prof. John Jose
- Level
- Undergraduate
- Language
- English
- Subjects
- Computer science, Engineering
- Source
- NPTEL
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- NPTEL gives no rating. Invisible Network shows it to Tweens profiles and older, judged from what the source says about it. How courses are placed
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