Learn · Design Verification and Test of Digital VLSI Circuits
Lecture 24 of 44Binary Decision Diagram
Ordered Binary Decision Diagram
Prof. Jatindra Kumar Deka and Dr. Santosh Biswas · IIT Guwahati
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- Design Verification and Test of Digital VLSI Circuits, IIT Guwahati (at NPTEL)
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All the lectures
- Introduction to Digital VLSI Design Flow
- High Level Design Representation
- Transformations for High Level Synthesis
- Introduction to HLS: Scheduling, Allocation and Binding Problem
- Scheduling Algorithms-1
- Scheduling Algorithms-2
- Binding and Allocation Algorithms
- Two level Boolean Logic Synthesis-1
- Two level Boolean Logic Synthesis-2
- Two level Boolean Logic Synthesis-3
- Heuristic Minimization of Two-Level Circuits
- Finite State Machine Synthesis
- Multilevel Implementation
- Introduction to formal methods for design verification
- Temporal Logic: Introduction and Basic Operators
- Syntax and Semantics of CTL
- Syntax and Semantics of CTL – Continued
- Equivalence between CTL Formulas
- Introduction to Model Checking
- Model Checking Algorithms I
- Model Checking Algorithms II
- Model Checking with Fairness
- Binary Decision Diagram: Introduction and construction
- Ordered Binary Decision Diagram
- Operation on Ordered Binary Decision Diagram
- Ordered Binary Decision Diagram for State Transition Systems
- Symbolic Model Checking
- Introduction to Digital VLSI Testing
- Functional and Structural Testing
- Fault Equivalence
- Fault Simulation-1
- Fault Simulation-2
- Fault Simulation-3
- Testability Measures (SCOAP)
- Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras
- D-Algorithm-1
- D-Algorithm-2
- ATPG for Synchronous Sequential Circuits
- Scan Chain based Sequential Circuit Testing-1
- Scan Chain based Sequential Circuit Testing-2
- Built in Self Test-1
- Built in Self Test-2
- Memory Testing-1
- Memory Testing-2