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Design Verification and Test of Digital VLSI Circuits

Prof. Jatindra Kumar Deka and Dr. Santosh Biswas · IIT Guwahati

Start with lecture 1 At NPTEL

Lectures

Introduction

  1. Introduction to Digital VLSI Design Flow Video
  2. High Level Design Representation Video
  3. Transformations for High Level Synthesis Video

Scheduling, Allocation and Binding

  1. Introduction to HLS: Scheduling, Allocation and Binding Problem Video
  2. Scheduling Algorithms-1 Video
  3. Scheduling Algorithms-2 Video
  4. Binding and Allocation Algorithms Video

Logic Optimization and Synthesis

  1. Two level Boolean Logic Synthesis-1 Video
  2. Two level Boolean Logic Synthesis-2 Video
  3. Two level Boolean Logic Synthesis-3 Video
  4. Heuristic Minimization of Two-Level Circuits Video
  5. Finite State Machine Synthesis Video
  6. Multilevel Implementation Video

Temporal Logic

  1. Introduction to formal methods for design verification Video
  2. Temporal Logic: Introduction and Basic Operators Video
  3. Syntax and Semantics of CTL Video
  4. Syntax and Semantics of CTL – Continued Video
  5. Equivalence between CTL Formulas Video

Verification Techniques

  1. Introduction to Model Checking Video
  2. Model Checking Algorithms I Video
  3. Model Checking Algorithms II Video
  4. Model Checking with Fairness Video

Binary Decision Diagram

  1. Binary Decision Diagram: Introduction and construction Video
  2. Ordered Binary Decision Diagram Video
  3. Operation on Ordered Binary Decision Diagram Video
  4. Ordered Binary Decision Diagram for State Transition Systems Video
  5. Symbolic Model Checking Video

Introduction to Digital Testing

  1. Introduction to Digital VLSI Testing Video
  2. Functional and Structural Testing Video
  3. Fault Equivalence Video

Fault Simulation and Testability Measures

  1. Fault Simulation-1 Video
  2. Fault Simulation-2 Video
  3. Fault Simulation-3 Video
  4. Testability Measures (SCOAP) Video

Combinational Circuit Test Pattern Generation

  1. Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras Video
  2. D-Algorithm-1 Video
  3. D-Algorithm-2 Video

Sequential Circuit Testing and Scan Chains

  1. ATPG for Synchronous Sequential Circuits Video
  2. Scan Chain based Sequential Circuit Testing-1 Video
  3. Scan Chain based Sequential Circuit Testing-2 Video

Built in Self test (BIST)

  1. Built in Self Test-1 Video
  2. Built in Self Test-2 Video
  3. Memory Testing-1 Video
  4. Memory Testing-2 Video

Syllabus and materials

At NPTEL, as the course publishes them.

Credits and licence

Institution
IIT Guwahati
Department
Computer Science and Engineering
Taught by
Prof. Jatindra Kumar Deka, Dr. Santosh Biswas
Level
Undergraduate
Language
English
Subjects
Computer science, Engineering
Source
NPTEL
Licence
CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
Attribution
NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
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