Learn · Synthesis of Digital Systems
Lecture 18 of 26Week 9
The Retiming Problem
Prof. Preeti Ranjan Panda · IIT Delhi
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- Synthesis of Digital Systems, IIT Delhi (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
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All the lectures
- Outline - What is Synthesis?
- Chip Design Flow and Hardware Modelling
- VHDL: Introduction to Hardware Description Languages & VHDL Basics
- VHDL: Modelling Timing - Events & Transactions
- VHDL: Specifying Hardware Behaviour with Processes
- VHDL: Specifying Structure, Test Benches, Parameterisation, & Libraries
- Introduction to High-level Synthesis
- Language front-end Design Representation
- Compiler Transformation in High Level Synthesis: Constant Folding, Dead Code Elimination, Constant Propagation, & Strength Reduction
- Memory Modelling & Compiler Transformation in High Level Synthesis: Common Sub-expression Elimination & Loop Invariant Code Motion
- Compiler Transformations in High Level Synthesis: Loop Unrolling and Function Inlining
- Hardware Transformations & ASAP / ALAP Scheduling
- Scheduling in High Level Synthesis: List Scheduling & Time-constrained Scheduling
- Force Directed Scheduling & Register Allocation
- High Level Synthesis and Timing Issues
- Finite State Machine Synthesis: Introduction to FSM Encoding
- Finite State Machine Synthesis: Identifyinh Common Cubes & Graph Embedding
- The Retiming Problem
- Efficient Solution to Retiming & Introduction to Logic Synthesis
- Binary Decision Diagrams
- Introduction to Logic Synthesis
- Two-level Logic Optimisation
- Multi-Level Logic Optimisation
- Multi-level Logic Synthesis: Technology Mapping
- Introduction to Timing Analysis
- Timing Analysis & Critical Paths