Course10610218126 lectures
Synthesis of Digital Systems
Prof. Preeti Ranjan Panda · IIT Delhi
Lectures
Week 1
Week 2
- VHDL: Introduction to Hardware Description Languages & VHDL Basics
- VHDL: Modelling Timing - Events & Transactions
Week 3
- VHDL: Specifying Hardware Behaviour with Processes
- VHDL: Specifying Structure, Test Benches, Parameterisation, & Libraries
Week 4
Week 5
- Compiler Transformation in High Level Synthesis: Constant Folding, Dead Code Elimination, Constant Propagation, & Strength Reduction
- Memory Modelling & Compiler Transformation in High Level Synthesis: Common Sub-expression Elimination & Loop Invariant Code Motion
Week 6
- Compiler Transformations in High Level Synthesis: Loop Unrolling and Function Inlining
- Hardware Transformations & ASAP / ALAP Scheduling
Week 7
- Scheduling in High Level Synthesis: List Scheduling & Time-constrained Scheduling
- Force Directed Scheduling & Register Allocation
- High Level Synthesis and Timing Issues
Week 8
Week 9
Week 10
Week 11
week 12
Syllabus and materials
At NPTEL, as the course publishes them.
Credits and licence
- Institution
- IIT Delhi
- Department
- Computer Science and Engineering
- Teacher
- Prof. Preeti Ranjan Panda
- Level
- Undergraduate
- Language
- English
- Subjects
- Computer science, Engineering
- Source
- NPTEL
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- NPTEL gives no rating. Invisible Network shows it to Tweens profiles and older, judged from what the source says about it. How courses are placed
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