Learn · Digital System design with PLDs and FPGAs
Lecture 18 of 44VHDL
Entity, Architecture and Operators
Prof. Kuruvilla Varghese · IISc Bangalore
Credits and licence
- From
- Digital System design with PLDs and FPGAs, IISc Bangalore (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- Teens profiles and older. How courses are placed
All the lectures
- Course Contents, Objective
- Revision of Prerequisite
- Design of Synchronous Sequential Circuits
- Analysis of Synchronous Sequential Circuits
- Top-down Design
- Controller Design
- Control algorithm and State diagram
- Case study 1
- FSM issues 1
- FSM Issues 2
- FSM Issues 3
- FSM Issues 4
- FSM Issues 5
- Synchronization 1
- Synchronization 2
- Case study 2
- Case study on FPGA Board
- Entity, Architecture and Operators
- Concurrency, Data flow and Behavioural models
- Structural Model, Simulation
- Simulating Concurrency
- Classes and Data types
- Concurrent statements and Sequential statements
- Sequential statements and Loops
- Modelling flip-flops, Registers
- Synthesis of Sequential circuits
- Libraries and Packages
- Operators, Delay modelling
- Delay modelling
- VHDL Examples
- VHDL coding of FSM
- VHDL Test bench
- VHDL Examples, FSM Clock
- Evolution of PLDs
- Simple PLDs
- Simple PLDs: Fitting
- Complex PLDs
- FPGA Introduction
- FPGA Interconnection, Design Methodology
- Xilinx Virtex FPGA’s CLB
- Xilinx Virtex Resource Mapping, IO Block
- Xilinx Virtex Clock Tree
- FPGA Configuration
- Altera and Actel FPGAs