Learn · Low Voltage CMOS Circuit Operation
Lecture 28 of 40Week 6
Decoder design considering INWE
Prof. Anand Bulusu · IIT Roorkee
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- Low Voltage CMOS Circuit Operation, IIT Roorkee (at NPTEL)
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- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
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All the lectures
- Introduction and motivation
- Review of MOSFET operation - I
- Review of MOSFET operation - II
- Basic charge model - I
- Basic charge model - II
- Basic charge model - III
- Basic charge model - IV
- Basic charge model - V
- Basic charge model - VI
- Basic charge model - VII
- Basic charge model - VIII
- Basic charge model - IX
- Basic charge model - X
- Minimum energy point -I
- Minimum energy point - II
- Minimum energy point - III
- Transistor sizing for combinational circuit - I
- Transistor sizing for combinational circuit - II
- Transistor sizing for asymmetric combinational circuits
- Charging and discharging mechanism in NTV combinational gates
- Effective current for NTV inverter
- Effective current for NTV combinational gates - I
- Effective current for NTV combinational gates - II
- Effective current for NTV combinational gates - III
- Combinational circuit design considering variations - I
- Combinational circuit design considering variations - II
- Buffer design considering INWE
- Decoder design considering INWE
- Flip - flop operation
- Warning flip-flops design and operation
- Single phase flip-flops design and operation
- Consideration of radiation effects in NTV
- Radiation – hardened NTV sequential circuit elements
- Level shifters for multi - Vdd domains
- Introduction to 6T SRAM
- Stability and Reliability Issues in 6T SRAM
- Read and Write-Assist Circuits in 6T SRAM
- Physical Insights into Channel Charge Distribution
- FinFET based Standard Cell Design
- Example problems