Lecture 3 of 37ARM Introduction and Pipeline structures
Processor core VS CPU core, ARM7TDMI Interface signals, Memory Interface, Bus Cycle types, Register set, Operational Modes
S.Chandramouleeswaran · IIT Madras
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- ARM Based Development, IIT Madras (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- Teens profiles and older. How courses are placed
All the lectures
- Types of computer Architectures, ISA's and ARM History
- Embedded System Software and Hardware, stack implementation in ARM, Endianness, condition codes
- Processor core VS CPU core, ARM7TDMI Interface signals, Memory Interface, Bus Cycle types, Register set, Operational Modes
- Instruction Format, ARM Core Data Flow Model, ARM 3 stage Pipeline, ARM family attribute comparision
- ARM 5 stage Pipeline, Pipeline Hazards, Data forwarding - a hardware solution
- ARM ISA and Processor Variants, Different Types of Instructions, ARM Instruction set, data processing instructions
- Shift Operations, shift Operations using RS lower byte, Immediate value encoding
- Dataprocessing Instructions
- AddressingMode-1, Addressing Mode -2
- Addressing Mode -2, LDR/STR, Addressing mode -3 with examples
- Instruction Timing, Addressing Mode - 4 with Examples
- Swap Instructions, Swap Register related Instructions, Loading Constants
- Program Control Flow, Control Flow Instructions, B & BL instructions, BX instruction
- Interrupts and Exceptions, Exception Handlers, Reset Handling
- Aborts, software Interrupt Instruction, undefined instruction exception
- Interrupt Latency, Multiply Instructions, Instruction set examples
- Thumb state, Thumb Programmers model, Thumb Implementation, Thumb Applications
- Thumb Instructions, Interrupt processing
- Interrupt Handelling schemes, Examples of Interrupt Handlers
- Coprocessors
- Coprocessor Instructions, data Processign Instruction, data transfers, register transfers
- Number representations, floating point representation
- Flynn's Taxonomy, SIMD and Vector Processors, Vector Floating Point Processor (VFP), VFP and ARM interactions, An example vector operation
- Memory Technologies, Need for memory Hierarchy, Hierarchical Memory Organization, Virtual Memory
- Cache Memory, Mapping Functions
- Cache Design, Unified or split cache, multiple level of caches, ARM cache features, coprocessor 15 for system control
- Processes, Memory Map, Protected Systems, ARM systems with MPU, memory Protection Unit (MPU)
- MMU Advantage, virtual memory translation, Multitasking with MMU, MMU organization, Tightly coupled Memory (TCM)
- Physical Vs Virtual Memory, Paging, Segmentation
- ARM Development Environment, Arm Procedure Call Standard (APCS),
- Example C program
- Embedded software Development, Image structure, linker inputs and outputs, memory map, application startup
- AMBA Overview, Typical AMAB Based Microcontroller, AHB bus features, AHB Bus transfers, APB bus transfers, APB bridge
- DMA, Peripherals, Programming Peripherals in ARM
- DMA:Direct Memory Access
- Protocols (I2c, SPI), UART, GPIO
- ARM ISAs, ARMv5, ARMv6, ARM v7, big.little technology, ARMv8