Learn · VLSI Data Conversion Circuits
Lecture 21 of 60VLSI Data Conversion Circuits
Linearized Analysis
Dr. Shanthi Pavan · IIT Madras
Credits and licence
- From
- VLSI Data Conversion Circuits, IIT Madras (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- Teens profiles and older. How courses are placed
All the lectures
- Introduction to Data Conversion
- Sampling-1
- Sampling-2
- Nonidealities in Samples
- Noise due to Sampling
- Distortion in a Sampling Switch
- Gate Boosted Switches-1
- Gate Boosted Switches-2
- Charge Injection
- S/H Characterization-1
- S/H Characterization-2
- FFTs and Leakage
- Spectral Windows-1
- Spectral Windows-2
- ADC/DAC Definition
- Quantization Noise-1
- Quantization Noise-2
- Over Sampling and Noise Shaping
- Delta-Sigma Modulation-1
- Delta-Sigma Modulation-2
- Linearized Analysis
- Stability of Delta Sigma Modulators
- High Order DSMs
- NTF Design and Tradeoffs
- Single bit Modulators
- Loop Filter Architectures
- Continous-time Delta Sigma Modulation
- Implicit Antialiasing
- Modulators with NRZ and Impulsive DACs
- High Order CTDSMs
- CTDM Design
- Excess Loop Delay (ELD)
- ELD Compensation
- Effect of Clock Jitter on CTDSMs-1
- Effect of Clock Jitter on CTDSMs-2
- Dynamic Range Scaling
- Simulation of CTDSMs
- Integrator Design-1
- Integrator Design-2
- Flash ADC Design
- Latches and Metastability
- Offset in a Latch-1
- Offset in a Latch-2 Auto Zeroing
- Auto Zeroing-2
- Auto Zeroing-3
- Auto Zeroing in flash ADCs
- Flash ADCs Case Study
- Flash ADC Case Study
- Flash ADC in a Delta Sigma Loop
- DAC Basics
- Binary and Themometer DACs
- Segmented DACs
- Optimal DAC Segmentation
- DAC Nonlinearities
- Current Steering DACs-1
- Current Steering DACs-2
- DAC Mismatches in DSMs
- Calibration and Randomization
- Dynamic Element Matching-1
- Dynamic Element Matching-2