Learn · CMOS Digital VLSI Design
Lecture 24 of 40Unit-5
Logical Efforts-III
Prof. Sudeb Dasgupta · IIT Roorkee
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- CMOS Digital VLSI Design, IIT Roorkee (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
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All the lectures
- MOS Transistor Basics-I
- MOS Transistor Basics-II
- MOS Transistor Basics-III
- MOS Parasitics and SPICE Model
- CMOS Inverter Basics-I
- CMOS Inverter Basics-II
- CMOS Inverter Basics-III
- Power Analysis-I
- Power Analysis-II
- SPICE Simulation-I
- SPICE Simulation-II
- Combinational Logic Design-I
- Combinational Logic Design-II
- Combinational Logic Design-III
- Combinational Logic Design-IV
- Combinational Logic Design-V
- Combinational Logic Design-VI
- Combinational Logic Design-VII
- Combinational Logic Design-VIII
- Combinational Logic Design-IX
- Combinational Logic Design-X
- Logical Efforts-I
- Logical Efforts-II
- Logical Efforts-III
- Sequential Logic Design -I
- Sequential Logic Design -II
- Sequential Logic Design -III
- Sequential Logic Design -IV
- Sequential Logic Design -V
- Sequential Logic Design -VI
- Sequential Logic Design -VII
- Sequential Logic Design -VIII
- Clocking Strategies for Sequential Design-I
- Clocking Strategies for Sequential Design-II
- Clocking Strategies for Sequential Design-III
- Clocking Strategies for Sequential Design-IV
- Sequential Logic Design -IX
- Clocking Strategies for Sequential Design-V
- Concept of Memory and its Designing-I
- Concept of Memory and its Designing-II