Learn · Memory Device Technology for AI/ML Computing
Lecture 49 of 60Week 10
10.3 AI/ML Computing: Bottlenecks of AI/ML Computing
Prof. Shubhadeep Bhattacharjee · IIT Hyderabad
Credits and licence
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- Memory Device Technology for AI/ML Computing, IIT Hyderabad (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge. Coordinated by IIT Madras.
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All the lectures
- 1.1 Evolving Computing Paradigms
- 1.2 Von-Neumann Architecture
- 1.3 Hierarchy and Classifications
- 1.4 Evolution of Memory Hierarchy with Device Technology
- 1.5 Classifications within Memory Hierarchy
- Practical Implementation of Memory Hierarchy
- Trends in the Global Memory Market Part 1
- Trends in the Global Memory Market Part 2
- Memory Array Architecture Part 1
- Memory Array Architecture Part 2
- 3.1 Memory Peripherals
- 3.2 Memory Footprint and Block Level Architecture
- 3.3 SRAM - Introduction
- 3.4 SRAM - Memory Effect & Hold Operation
- 3.5 SRAM - Read Operation Part 1
- 3.6 SRAM - Read Operation Part 2
- 4.1 SRAM - Write Operation
- 4.2 SRAM - Noise Margin Analysis
- 4.3 SRAM - Read, Write Conflict & Scaling
- 4.4 DRAM - Introduction
- 4.5 DRAM - Subsystem Architecture
- 5.1 DRAM - Cell Architecture & Hold Operation
- 5.2 DRAM - Refresh, Charge Transfer Ratio.
- 5.3 DRAM- Read, Write & Restore
- 5.4 DRAM - Scaling Challenges and Solutions
- 5.5 NAND Flash - Introduction
- 6.1 NAND Flash - Flash Cell Architecture
- 6.2 NAND Flash - Array Architecture
- 6.3 NAND Flash - Program Operation
- 6.4 NAND Flash - Erase and Read Operations
- 6.5 NAND Flash - Bit Scaling
- 7.1 NAND Flash - Scaling Challenges & Solutions
- 7.2 Recap of Part 1
- 7.3 eNVMs Fundamentals of two-terminal Memristors
- 7.4 eNVMs PCRAMs Fundamentals of Phase Change Memories
- 7.5 eNVMs PCRAMs Technology and commercialization
- 8.1 eNVMs RRAMs Fundamentals
- 8.2 eNVMs RRAMs VCRAM and CBRAM
- 8.3 eNVMs RRAMs - Performance Metrics & Commercialization
- 8.4 eNVMs MRAM spin GMR TMR
- 8.5 eNVM MRAMs Field and STT MRAM
- 9.1 eNVM MRAM SOT and Commercialization
- 9.2 AI/ML Computing: Introduction & History
- 9.3 AI/ML Computing: Artificial Neural Networks
- 9.4 AI/ML Computing: Working of ANNs
- 9.5 AI/ML Computing: Backpropagation, Inference and Architectures in ANNs
- 10.1: AI/ML Computing: Convolution
- 10.2 AI/ML Computing: Convolutional Neural Networks
- 10.3 AI/ML Computing: Bottlenecks of AI/ML Computing
- 10.4: Neuromorphic Computing: Introduction
- 10.5: Neuromorphic Computing: The Biological Insipration
- 11.1: Neuromorphic Computing: Implementation of Neurons in Hardware
- 11.2: Neuromorphic Computing: Synaptic Plasticity
- 11.3: Neuromorphic Computing: Hardware Implementation of Synapses
- 11.4: SNNs & IMC: Operations in a Spiking Neural Network
- 12.1: SNNs & IMC: Unsupervised & Supervised Training of SNNs
- 12.2: SNNs & IMC: Implementations of SNNs
- 12.3: SNNs & IMC: Digital In-Memory Computing
- 12.4: SNNs & IMC: Analog In-Memory Computing
- 12.5: Overview, Roadmap & Acknowledgements