Learn · Analog Electronic Circuits - IITM
Lecture 74 of 84week-11
Phase Margin Example
Prof. Shanthi Pavan · IIT Madras
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All the lectures
- Introduction Linear and Nonlinear Network
- Small Signal Analysis of Nonlinear Networks
- Small Signal Analysis
- Incremental Model for Common Two Terminal Element Passive Two Terminal Elements
- Linear and Nonlinear Two Ports and the Incremental Y Matrix
- Graphical Representation of the Y Matrix
- Nonlinear Two Ports With Incremental Gain
- IV Charateristic of a Nonlinear 2 port with Incremental Gain
- The MOSFET and its Characterisitics
- Deriving the Common V Source Amplifier Part 1
- The Common Source Amplifier
- Large Signal Behaviour of the Common Source Amplifier
- The Common Source Amplifier Swing Limits
- Introduction to Robust Biasing
- Robust Biasing Part 1 Common Source Amplifier with DC Drain Feedback
- Robust Biasing with the Current Mirror and Drain Gate Resistor
- Robust Baising With Source Feedback Part 1
- Robust Biasing with Source Feedback - Part 2
- Robust Biasing with Source Degeneration
- Introduction to Negative Feedback
- The Ideal Operational Amplifier
- Negative Feedback Continued
- Robust Baising with Drain Measurement and Source Feedback
- Robust biasing with source measurement and gate feedback
- The Incremental Voltage Controlled Voltage Source The Common drain Amplifier Incremental Picture
- Baising of the Common Drain Amplifier and Signal Swings
- The VCVS Continued, the Incremental
- Introducing the Current Controlled Voltage Source
- The Incremental Current Controlled Voltage Source Transimpedance Amplifier
- The Transimpedance amplifier contd
- The Incremental current controlled current source, the common gate amplifier
- Summary of controlled Sources and finite output Impedance of the Transistor
- Effect of Finite Output Resistance on Basic Building Block Part 1
- Effect of Finite Output Resistance on The Building Blocks Part 2
- Effect of Finite Output Resistance on the Basic Building Block Part 3
- Finite output Effect in current Mirrors the Cascode Current Mirror
- Comparison of Current Mirrors The High Swing Cascode
- Precision High Swing Cascode
- The PMOS transistor
- Small Signal Model and Bias Stabilization
- Basic Building Blocks with PMOS Devices
- Fixed Transconductance Bias Circuits from First Principles
- Limitation of a Resistive Load
- The Active Load
- The Active Load (contd)
- The CMOS Inverter
- The CMOS Inverter (contd)
- The Differential Amplifier
- Half - Circuit Analysis
- The Different Amplifier with Active Load - Part 1
- The Different Amplifier with Active Load - Part 2
- Large Signal Behaviour of the Different Pair
- The two Stage Opamp and Single Supply Operation
- The two Stage Opamp (contd)
- The Two Stage Opamp contd
- Swing Limits of the Two Stage OTA
- The Two-Stage Opamp
- The Bandgap Reference Principle
- The Bandgap Reference - Part 1
- The Bandgap Reference - Part 2
- Memory Effects in MOS Transistors
- The Common Source Amplifier with Parasitic Capacitances
- The Common Source Amplifier with Parasitic Capacitances
- Frequency Response of the Common Drain Amplifier
- Frequency Response of the Common Gate Amplifier
- Stability of Negative Feedback System The First Order Forward Amplifier
- Stabilty of Second Order Feedback System
- Stability of Third Order Negative Feedback System
- Dominant Pole Compensation - Part 1
- Dominant Pole Cpmpensation - Part 2
- Phase Margin
- Example Phase Margin Caculations
- Dominant Pole Compensation Summary
- Phase Margin Example
- The 2 Stage Miller Compensated Amplifier
- 2 Stage Operational Amplifier and Miller Compensation (Cond)
- Intuition Behind the Dominant and Second Poles in a Miller Compensated OTA
- 2 Stage Operational Amplifier and Miller Compensation Cancelling the RHP Zero
- Miller Compensation OTA Schematic
- Bipolar Junction Transistor Circuits-Device Equations and Small Signal Model
- BJT Biasing and Basic Building Blocks
- Bipolar Junction Transistor Circuits Swing Limits and Two Stage Opamp
- Input Stage of the 741 Opamp
- Basic Analysis of the 741