Lecture 9 of 83week-02
Transistor - 8 - Sub-Threshold Leakage
Prof. Janakiraman · IIT Madras
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- Digital IC Design, IIT Madras (at NPTEL)
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All the lectures
- Introduction - Digital IC Design
- Transistor - 1 - PN Junction
- Transistor - 2 - MOS Capacitor Threshold Voltage
- Transistor - 3 - MOS Transistor Current Expression
- Transistor- 4 - Body Effect and I-V Plots
- Transistor -5 - Short Channel Transistors - Channel Length Modulation
- Transistor- 6 - Velocity Saturation and Level-1 SPICE Model
- Transistor - 7 - Drain Induced Barrier Lowering
- Transistor - 8 - Sub-Threshold Leakage
- Transistor-9 - Substrate and Gate Leakage
- Transistor - 10 - The PMOS Transistor
- Transistor-11 - Transistor Capacitance - 1
- Transistor - 12 - Transistor Capacitance - 2
- Inverter - 1 - CMOS Inverter Construction
- Inverter - 2 - Voltage Transfer Characteristics
- Inverter - 3 - Load Line Analysis
- Inverter - 4 - Trip Point for Short Channel Device Inverter
- Inverter-5 - Trip Point for Long Channel Device Inverter
- Inverter - 6 - Noise Margin Analysis-1
- Inverter - 7 - Noise Margin Analysis-2
- Inverter-8 - Noise Margin Analysis-3
- Inverter - 9 - Noise Margin Analysis-Long Channel Device Inverter-1
- Inverter - 10 - Noise Margin Analysis-Long Channel Device Inverter-2
- Inverter - 11 - Pass Transistors
- Inverter - 12 - NMOS Transistor ON Resistance and Fall Delay
- Inverter - 13 - Elmore Delay Model
- Inverter - 14 - Inverter: Transient Response
- Inverter - 15 - Inverter: Dynamic Power
- Inverter - 16 - Inverter: Short Circuit Power
- Inverter - 17 - Inverter: Leakage Power and Transistor Stacks
- Inverter - 18 - Stacking Effect and Sleep Transistors
- Inverter - 19 - Ring Oscillators and Process Variations
- CombCkt - 1 - Implementing Any Boolean Logic Function
- CombCkt - 2 - Implementing Any Boolean Logic Function: Examples. Gate sizing
- CombCkt - 3 - Gate Sizing
- CombCkt - 4 - Logic Gate Capacitance
- CombCkt - 5 - Gate Delay
- CombCkt - 6 - Parasitic Delay
- CombCkt - 7 - Gate Delay with a Load Capacitance
- CombCkt - 8 - Logical Effort
- CombCkt - 9 - Gate Delay
- CombCkt - 10 - Path Delay Calculation and Optimization Formulation
- CombCkt - 10A - Path Delay Optimization: Intuition
- CombCkt - 10B - Path Delay Optimization: Example
- CombCkt - 11 - Buffer Insertion
- CombCkt - 12 - Input Ordering and Asymmetric Gates
- CombCkt - 13 - Skewed Gates
- CombCkt - 14 - Special Functions
- CombCkt - 15 - Pseudo NMOS Logic
- CombCkt - 16 - Pseudo NMOS Inverter
- CombCkt - 17 - Pseudo NMOS Logical Effort and CVSL
- CombCkt - 18 - Dynamic Circuits and Input Monotonicity
- CombCkt - 19 - Domino Logic and Weak Keepers
- CombCkt - 20 - Transmission Gate Logic
- CombCkt - 21 - Gate Sizing for Large Circuits
- AM - 1 - Ripple Adder Introduction
- AM - 2 - Full Adder Circuit Implementation
- AM - 3 - Full Adder Optimization
- AM - 4 - Carry Skip Adder
- AM - 5 - Carry Select Adder
- AM - 6 - Linear and Square Root Carry Select Adder
- AM - 7 - Two's Complement Arithmetic
- AM - 8 - Two's Complement Sign Extension
- AM - 9 - Array Multiplier
- AM - 10 - Array Multiplier - Timing Analysis
- AM - 11 - Carry Save Multiplier
- AM - 12 - Carry Save Multiplier - Signed Multiplication
- SeqCkt - 1 - Introduction to Pipelining
- SeqCkt - 2 - Time Borrowing
- SeqCkt - 3 - Master Slave Flip Flop
- SeqCkt - 4 - Flop Timing Parameters
- SeqCkt - 5 - Alternate Circuit Implementations
- SeqCkt - 6 - Clock Overlap
- SeqCkt - 7 - C2MOS Flop
- SeqCkt - 8 - Flop Characterization
- SeqCkt - 9 - Max and Min Delay of Flop Based Systems
- SeqCkt - 10 - Flop Min Delay Constraint
- SeqCkt - 11 - Latch - Max and Min Delay Constraints
- SeqCkt - 12 - Latch-Timing Analysis with Skew
- SeqCkt - 13 - Time Borrowing
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