Learn · Digital Electronic Circuits
Lecture 54 of 65WEEK 11
Lecture 54 : Analog to Digital Conversion - II
Prof. Goutam Saha · IIT Kharagpur
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All the lectures
- Lecture 01: Introduction
- Lecture 02: Transistor as a switch
- Lecture 03: Performance Issues and Introduction to TTL
- Lecture 04: Transistor Transistor Logic (TTL)
- Lecture 05: CMOS Logic
- Lecture 06: Basic Gates and their representations
- Lecture 07: Fundamentals of Boolean Algebra
- Lecture 08: Boolean Function to Truth Table and Implementaion Issues
- Lecture 09: Truth Table to Boolean Function and Implementaion Issues
- Lecture 10: Karnugh Map and Digital Circuit Realization
- Lecture 11: Karnaugh Map to Entered Variable Map
- Lecture 12: Quine - McClusky (QM) Algorithm
- Lecture13: Cost Criteria and Minimization of Multiple Output Functions
- Lecture 14: Static 1 Hazard
- Lecture 15: Static 0 Hazard and Dynamic Hazard
- Lecture 16 : Multiplexer: Part I
- Lecture 17 : Multiplexer: Part II
- Lecture 18 : Demultiplexer / Decoder
- Lecture 19 : Decoder with BCD Input and Encoder
- Lecture 20 : Parity Generator and Checker
- Lecture 21 : Number System
- Lecture 22 : Negative Number and 2's Complement Arithmetic
- Lecture 23 : Arithmetic Building Blocks - I
- Lecture 24 : Arithmetic Building Blocks - II
- Lecture 25 : Overflow Detection and BCD Arithmetic
- Lecture 26 : Magnitude Comparator
- Lecture 27 : Arithmetic Logic Unit (ALU)
- Lecture 28 : Unweighted Code
- Lecture 29 : Error Detection and Correction Code
- Lecture 30 : Multiplication and Division
- Lecture 31: SR Latch and Introduction to Clocked Flip-Flop
- Lecture 32: Edge-Triggered Flip-Flop
- Lecture 33: Representations of Flip-Flops
- Lecture 34: Analysis of Sequential Logic Circuit
- Lecture 35: Conversion of Flip-Flops and Flip-Flop Timing Parameters
- Lecture 36: Register and Shift Register: PIPO and SISO
- Lecture 37: Shift Register: SIPO, PISO and Universal Shift Register
- Lecture 38: Application of Shift Register
- Lecture 39: Linear Feedback Shift Register
- Lecture 40: Serial Addition, Multiplication and Division
- Lecture 41: Asynchronous Counter
- Lecture 42: Decoding Logic and Synchronous Counter
- Lecture 43: Cascading: Mod 2, 3, 5 to Mod 6, 10, 1000 Counter
- Lecture 44: Counter Design with Asynchronous Reset and Preset
- Lecture 45: Counter Design as Synthesis Problem and Few Other Uses of Counter
- Lecture 46 : Synthesis of Sequential Logic Circuit: Moore Model and Mealy Model
- Lecture 47 : Moore Model and Mealy Model: Realization of Digital Logic Circuit
- Lecture 48 : Algorithmic State Machine (ASM) Chart and Synthesis of Sequential Logic Circuit
- Lecture 49 : Circuit Realization from ASM Chart and State Minimization
- Lecture 50 : State Minimization by Implication Table and Partitioning Method
- Lecture 51 : Digital to Analog Conversion - I
- Lecture 52 : Digital to Analog Conversion - II
- Lecture 53 : Analog to Digital Conversion - I
- Lecture 54 : Analog to Digital Conversion - II
- Lecture 55 : Certain Performance Issue of ADC and DAC
- Lecture 56: Introduction to Memory
- Lecture 57: Static Random Access Memory (SRAM)
- Lecture 58: Dynamic RAM(DRAM) and Memory Expansion
- Lecture 59: Read Only Memory (ROM)
- Lecture 60: PAL, PLA, CPLD, FPGA
- Live Session 06-03-2021
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- Live Session 03-02-2022
- Live Session 23-03-2022
- Live Session 22-02-2024