Learn · Computer Organization and Architecture
Lecture 6 of 52Week 2
Fast Multiplier Circuit (Contd.)
Prof. Kamakoti · IIT Madras
Credits and licence
- From
- Computer Organization and Architecture, IIT Madras (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- Tweens profiles and older. How courses are placed
All the lectures
- Introduction High Speed Circuit - Design Recursive Doubling
- High Speed Circuit Design - Fast Adder Circuits
- Lab 1 : Introduction
- Fast Adder Circuits (Contd.)
- Fast Multiplier Circuit
- Fast Multiplier Circuit (Contd.)
- Programming using X86 ISA - Addressing Modes
- Programming using X86 ISA - Addressing Modes
- Floating point - Precision and Accuracy
- Floating Point - Addition, Subtraction and Multiplication
- Instruction Set Architecture
- Instruction Set Architecture (Continued)
- Lab 2 : Segmentation
- Lab 2 : Segmentation-Part II
- Lab 2 : Segmentation-Part III
- Orthogonal ISA, C Constructs Mapping, Addressing Modes
- Atomic and Predicated Instructions
- Atomic and Predicated Instructions ( Contd.)
- General Purpose Registers
- Expanding opcodes
- Introduction to Pipelining
- Pipelining
- Data Hazards
- Lab 2: Instruction Scheduling - Static and Dynamic
- Dynamic Instruction Scheduling
- Dynamic Instruction Scheduling (Contd..)
- Control Hazard, Branch Prediction
- Process Management
- Branch prediction
- Global Branch Prediction
- Structural Hazard, Architectural Enhancements
- Lab 3: Virtual Memory
- Locality of Reference, Demand paging
- Page Replacement Algorithm
- Multilevel Paging, Translational Lookaside Buffer
- Multilevel Paging
- Multilevel Paging-Part 1
- Page Frame Allocation, Beledy's Anomaly
- Paging, Cache
- Cache
- Cache Organisation
- Cache - Cache Coherency, Dual Ported Cache
- Multilevel Caching, Multitasking
- Cache, Degree of Multiprogramming
- Shared Memory Architecture
- Shared Memory Architecture-Part I
- Virtually Indexed - Virtually Tagged and Physically Tagged Caches
- Lab 4 : Task Switching ( Contd)
- Shared Memory Architecture, Cache Coherence
- Concurrent Programming in Hardware
- Concurrent Programming in Hardware-Part II
- Conclusion : Recent Trends in Computer Organization & Architecture