Lecture 20 of 33Instruction Level Parallelism
Compiler optimizations for Exposing ILP
Prof. Madhu Mutyam · IIT Madras
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- Computer Architecture, IIT Madras (at NPTEL)
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- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
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All the lectures
- Introduction to Computer Architecture
- Quantitative Principles of Computer Design
- Instruction Set Principles-Part 1
- Instruction Set Principles-Part 2
- Instruction Set Principles-Part 3
- Cache Memory Hierarchy - Part 1
- Cache Memory Hierarchy - Part 2
- Cache Memory Hierarchy - Part 3
- Cache Memory Hierarchy - Part 4
- Main Memory Design - Part 1
- Main Memory Design - Part 2
- Main Memory Design - Part 3
- Fundamentals of Pipelining - Part 1
- Fundamentals of Pipelining - Part 2
- Fundamentals of Pipelining - Part 3
- Fundamentals of Pipelining - Part 4
- Fundamentals of Pipelining - Part 5
- Scalar to Superscalar pipeline
- Instruction Dependencies
- Compiler optimizations for Exposing ILP
- Advanced Branch Prediction Techniques - Part 1
- Advanced Branch Prediction Techniques - Part 2
- Superscalar Organization
- Register Renaming
- Tomasulo Algorithm
- Dynamic Execution Core
- Multi threading
- Multicore Processor Architecture
- Cache Coherence
- Cache Coherence Protocol Design
- Synchronization
- Memory Consistency - Part 1
- Memory Consistency - Part 2