Learn · Embedded Systems Design
Lecture 12 of 49Week 3
Lecture 12: Tutorial - IV
Prof. Anupam Basu · IIT Kharagpur
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- Embedded Systems Design, IIT Kharagpur (at NPTEL)
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All the lectures
- Lecture 1: Introduction
- Lecture 2: Processors
- Lecture 3: General Purpose and ASIPs Processor
- Lecture 4: Designing a Single Purpose Processor
- Lecture 5: Optimization Issues
- Lecture 6: Introduction to FPFA
- Lecture 7: FPGA Contd.
- Lecture 8: Behaviour Synthesis on FPGA using VHDL
- Lecture 9: Tutorial - I
- Lecture 10 : Tutorial - II
- Lecture 11: Tutorial - III
- Lecture 12: Tutorial - IV
- Lecture 13: Sensors and Signals
- Lecture 14: Discretization of Signals and A/D Converter
- Lecture 15: Quantization Noise, SNR and D/A Converter
- Lecture 16: Arduino Uno
- Lecture 17: Arduino Uno (Contd.), Serial Communication and Timer
- Lecture 18: Controller Design using Arduino
- Lecture 19: Tutorial - V
- Lecture 20:Power Aware Embedded System - I
- Lecture 21: Power Aware Embedded System - II
- Lecture 22: SD and DD Algorithm
- Lecture 23: Parallel Operations and VLIW
- Lecture 24: Code Efficiency
- Lecture 25: DSP Application and Address Generation Unit
- Lecture 26: Real Time O.S - I
- Lecture 27: Real Time O.S - II
- Lecture 28: RMS Algorithm
- Lecture 29 : EDF Algorithm and Resource Constraint Issue
- Lecture 30 : Priority Inversion and Priority Inheritance Protocol
- Lecture 31 : Modeling and Specification - I
- Lecture 32 : Modeling and Specification - II
- Lecture 33 : FSM and Statechart
- Lecture 34 : Statechart and Statemate Semantics
- Lecture 35 : Statecharts (Contd.)
- Lecture 36 : Program State Machines
- Lecture 37 : SDL
- Lecture 38 : Data Flow Model - I
- Lecture 39 : Data Flow Model - II
- Lecture 40 : Hardware Synthesis - I
- Lecture 41 : Hardware Synthesis - II
- Lecture 42 : Scheduling
- Lecture 43 : Digital Camera Design
- Lecture 44 : Digital Camera - Iterative Design
- Lecture 45 : HW-SW Partitioning
- Lecture 46 : Optimization - I
- Lecture 47 : Optimization - II
- Lecture 48 : Simulation
- Lecture 49 : Formal Verification