Learn · High Performance Computer Architecture
Lecture 14 of 41Dynamic Instruction Scheduling
Dynamic Instruction Scheduling (Contd.)
Prof. Ajit Pal · IIT Kharagpur
Credits and licence
- From
- High Performance Computer Architecture, IIT Kharagpur (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
- Who can watch
- Tweens profiles and older. How courses are placed
All the lectures
- Introduction and Course Outline
- Performance
- Instruction Set Architecture
- MIPS ISA Processor
- MIPS ISA Processor (Contd.)
- Pipelining Introduction
- Instruction Pipelining
- Pipeline Hazards
- Data Hazards
- Software Pipelining
- In Quest of Higher ILP
- In Quest of Higher ILP (Contd.)
- Dynamic Instruction Scheduling
- Dynamic Instruction Scheduling (Contd.)
- Control Hazards
- Branch Prediction
- Branch Prediction (Contd.)
- Dynamic Instruction Scheduling with Branch Prediction
- Hardware Based Speculation
- Tutorial - I
- Hierarchical Memory Organization
- Hierarchical Memory Organization (Contd.)
- Hierarchical Memory Organization (Contd.)
- Hierarchical Memory Organization (Contd.)
- Cache Optimization Techniques (Contd.)
- Cache Optimization Techniques (Contd.)
- Main Memory Organization
- Main Memory Optimizations
- Virtual Memory
- Virtual Memory (Contd.)
- Virtual Machines
- Storage Technology
- Storage Technology (Contd.)
- Case Studies
- Case Studies (Contd.)
- Case Studies (Contd.)
- Multithreading and Multiprocessing
- Simultanoues Multithreading
- Symmetric Multiprocessors
- Distributed Memory Multiprocessors
- Cluster, Grid and Cloud Computing