Learn · Advanced Computer Architecture
Lecture 29 of 36Tiled Chip Multicore Processors
Lec 20: Tiled Chip Multicore Processors
Prof. John Jose · IIT Guwahati
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- Advanced Computer Architecture, IIT Guwahati (at NPTEL)
- Licence
- CC BY-NC-SA, as NPTEL states it. Non-commercial use only.
- Attribution
- NPTEL states: "Distributed under Creative Commons Attribution-ShareAlike / CC BY - NC - SA", beside a BY-NC-SA badge.
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All the lectures
- Review of Basic Computer Organization
- Perfomance Evaluation Methods
- Introduction to RISC Instruction Pipeline
- Instruction Pipeline & Performance
- Lec 4: Pipeline Hazards
- Lec 5 : Control Hazards & Branch Prediction
- Lec 6 : MIPS Pipeline for Multi-Cycle Operations
- Tutorial 2 : Pipeline Hazard Analysis
- Lec 7: Compiler Techniques to Explore ILP
- Lec 8: Dynamic Scheduling to Explore ILP
- Lec 9: Dynamic Scheduling with Tomasulo's Algorithm
- Lec 10: Dynamic Scheduling with Speculative Execution
- Tutorial 3: Static and Dynamic Scheduling
- Lec 11: Advanced Pipelining & Superscalar Processors
- Lec 12: Exploiting DLP: Vector & GPU Architectures
- Tutorial 4: Architectural Simulation using gem5
- Tutorial 5: Core Optimization in gem5
- Lec 13: Introduction to Cache Memory
- Lec 14: Block Replacement Techniques & Write Strategy
- Tutorial 6: Design Concepts in Cache Memory
- Lec 15: Optimization Techniques in Cache Memory
- Lec 16: Advanced Cache Optimization Techniques
- Tutorial 7: Optimization Techniques in Cache Memory
- Tutorial 8: Cache Optimization in gem5
- Lec 17: Introduction to DRAM System
- Lec 18: DRAM Controllers & Address Mapping
- Lec 19: Secondary Storage Systems
- Tutorial 9: Design Concepts in DRAM and Harddisk
- Lec 20: Tiled Chip Multicore Processors
- Lec 21: Routing Techniques in Network on Chip
- Lec 22: NoC Router Microarchitecture
- Lec 23: How to Explore Computer Architecture?
- Tutorial 10: TCMP and NoC Design Principles
- Live Session 30-03-2021
- Live Session 24-09-2019
- Live Session 30-08-2019