Lecture 9 of 272006-02-221 h 25 min
Dynamic Logic (con't)
Jan Rabaey · University of California, Berkeley
Credits and licence
- From
- EE 241 - Spring 2006, University of California, Berkeley (at Internet Archive)
- Licence
- Internet Archive states no licence for it.
- Attribution
- 2006 Regents of the University of California
- Who can watch
- Teens profiles and older. How courses are placed
All the lectures
- Course Introduction
- Optimization for Performance
- Scaling
- Modeling
- Device Models
- Static and Pass Transistor Logic
- Dynamic Logic
- Logic Families for Performance; Dynamic Logic
- Dynamic Logic (con't)
- Low Power Design
- Low Power - Supply Voltage Selection
- Active Power-Reducing Switching Capacitance; Managing Leakage
- Leakage+Adiabatic
- Adiabatic (con't); Ultra Low Voltage Design
- Ultra-Low Voltage Design (Makeup Lecture for March 6, 2006)
- Process Variations
- Process Variations; Power Distribution
- Timing
- Timing & Asynchronous
- Asynchronous & Synchronization
- Clock Distribution
- Embedded Memory
- Low Voltage Memory
- Memory (con't)
- Tests
- Semester Look Back
- Project Presentations