Architecting FPGA for low power Leadership

Name: Architecting FPGA for low power Leadership
Duration: 25 min 54 s
Channel: Hardik Shah

Hardik Shah · CERN

Credits and licence

From: Architecting FPGA for low power Leadership, CERN (at CERN)
Licence: CERN, as CERN states it.
Attribution: © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
Who can watch: Tweens profiles and older. How courses are placed