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Talk26 min

Architecting FPGA for low power Leadership

Hardik Shah · CERN

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About

Reducing power consumption in FPGAs offers a range of benefits across various applications, including: extended battery life, simplified heat sink requirements, reduced complexity of the PCB power network, the potential for smaller package sizes, minimized heat-related measurement errors, and increased component longevity. Achieving energy-efficient FPGA design demands a comprehensive approach—from product strategy to the choice of process technology and on-chip architecture. In this talk, the speaker will provide an inside look at how Lattice FPGAs are engineered to deliver significant power savings..

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The talk

  1. Architecting FPGA for low power Leadership 2025-05-22 · 26 min · CERN's player

Credits and licence

Institution
CERN
Department
FPGA Developers' Forum (FDF)
Speaker
Hardik Shah
Year
2025
Language
English
Subjects
Business and management
Source
CERN
Licence
CERN, as CERN states it. CERN's terms
Attribution
© CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
Who can watch
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