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Porting MADGRAPH to FPGA using High-Level Synthesis (HLS)

Hector Gutierrez Arance · CERN

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About

The escalating demand for data processing in particle physics research has spurred the exploration of novel technologies to enhance efficiency and speed of calculations. This study presents the development of a port of MADGRAPH, a widely used tool in particle collision simulations, to FPGA using High-Level Synthesis (HLS). Experimental evaluation is ongoing, but preliminary assessments suggest a promising enhancement in calculation speed compared to traditional CPU implementations. This potential improvement could enable the execution of more complex simulations within shorter timeframes. This study describes the complex process of adapting MADGRAPH to FPGA using HLS, focusing on optimizing algorithms for parallel processing. These advancements could enable faster execution of complex simulations, highlighting FPGA's crucial role in advancing particle physics research..

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The talk

  1. Porting MADGRAPH to FPGA using High-Level Synthesis (HLS) 2024-06-12 · 17 min · CERN's player

Credits and licence

Institution
CERN
Department
FPGA Developers' Forum (FDF)
Speaker
Hector Gutierrez Arance
Year
2024
Language
English
Source
CERN
Licence
CERN, as CERN states it. CERN's terms
Attribution
© CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
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